In recent years, much attention has
been focused on two-dimensional
(2D) material-based synaptic transistor devices because of their inherent
advantages of low dimension, simultaneous read–write operation
and high efficiency. However, process compatibility and repeatability
of these materials are still a big challenge, as well as other issues
such as complex transfer process and material selectivity. In this
work, synaptic transistors with an ultrathin organic semiconductor
layer (down to 7 nm) were obtained by the simple dip-coating process,
which exhibited a high current switch ratio up to 106,
well off state as low as nearly 10–12 A, and low
operation voltage of −3 V. Moreover, various synaptic behaviors
were successfully simulated including excitatory postsynaptic current,
paired pulse facilitation, long-term potentiation, and long-term depression.
More importantly, under ultrathin conditions, excellent memory preservation,
and linearity of weight update were obtained because of the enhanced
effect of defects and improved controllability of the gate voltage
on the ultrathin active layer, which led to a pattern recognition
rate up to 85%. This is the first work to demonstrate that the pattern
recognition rate, a crucial parameter for neuromorphic computing can
be significantly improved by reducing the thickness of the channel
layer. Hence, these results not only reveal a simple and effective
way to improve plasticity and memory retention of the artificial synapse
via thickness modulation but also expand the material selection for
the 2D artificial synaptic devices.