Solutions to heavy ion induced avalanche burnout in power devices

Wrobel, T. F.; Beutler, D.E.

doi:10.1109/23.211346

Cited by 42 publications

(13 citation statements)

References 7 publications

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“…If the applied voltage is not removed from the device quickly, simultaneous high currents and high voltages induce second breakdown of the parasitic bipolar transistor and can result in meltdown of the device. There have been many models to describe this mechanism [1,[7][8][9]. However, none of these models includes the physical destruction of the device caused by thermal processes.…”

Section: Seb In Power Mosfetsmentioning

confidence: 98%

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Single event burnout in power diodes: Mechanisms and models

Albadri

Schrimpf

Galloway

et al. 2006

Microelectronics Reliability

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Section: Seb In Power Mosfetsmentioning

confidence: 98%

“…This breakdown was attributed to the turn-on of a parasitic BJT inherent to the MOSFET structure [8]. The failure mechanism was described based on the current induced avalanche (CIA) model [7] as a result of the base push-out phenomenon [10]. Hohl and Johnson proposed a model that explains the regenerative feedback mechanism [11].…”

Section: Seb In Power Mosfetsmentioning

confidence: 99%

Single event burnout in power diodes: Mechanisms and models

Albadri

Schrimpf

Galloway

et al. 2006

Microelectronics Reliability

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“…Under the four beam conditions tested, these devices reached their regular avalanche condition before SEB was observed. The SEB mechanism has been described, in detail, in many publications [7]- [15]. Hohl and Johnson [10] presented this description of the SEB mechanism in 1989.…”

Section: Sample Preparation and Test Proceduresmentioning

confidence: 97%

Evaluation of Worst-Case Test Conditions for SEE on Power DMOSFETs

Liu¹,

Boden²,

Cao³

et al. 2006

2006 IEEE Radiation Effects Data Workshop

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Extensive single event effects tests were performed on a new generation, the R6 process, of radiation-hardened 600-volt and 250-volt power metal-oxide semiconductor fieldeffect transistors (MOSFETs) from International Rectifier using two different ions (Krypton and Xenon) at many different beam energies, Bragg Peak positions, and drain and gate biases. Results show that there is no worst-case test condition for single event burnout but positioning of the energy deposition is critical for single event gate rupture.

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“…Wrobel et al proposed the current induced avalanche (CIA) breakdown phenomenon for SEB mechanism [3]. According to the CIA model, epi-layerhbstrate junction must be broken-down with high density current along the ion track.…”

Section: Epics Spectra and Its Interpretationmentioning

confidence: 99%