Solving linear, min and max constraint systems using CLP based on relational interval arithmetic

Girodias, P.; Cerny, Eduard; Older, William J.

doi:10.1007/3-540-60299-2_12

Cited by 3 publications

(4 citation statements)

References 7 publications

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“…A natural extension of the approach is to include the latest constraints ] in addition to the linear constraints. They are by their nature causal, and efficient methods exist for computing the shortest distances over linear and latest constraint systems [McMillan and Dill 1992;Girodias et al 1995]. The inclusion of earliest constraint makes the problem of computing time distances between actions NP-complete [McMillan and Dill 1992]; however, as shown in Girodias et al [1995], we can use CLP (BNR) Prolog and its power of relational interval arithmetic to solve the constraint satisfaction problem and to perform the necessary exploration and backtracking.…”

Section: Resultsmentioning

confidence: 98%

Semantics and verification of action diagrams with linear timing

Khordoc

Cerny

1998

ACM Trans. Des. Autom. Electron. Syst.

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Specifications containing linear timing constraints, such as found in action diagrams (timing diagrams) defining interface behaviors, are often used in practice. Although efficient O(n 3 ) shortest path algorithms exist for computing the minimum and maximum time distances between actions, subject to the timing constraints, there is so far no accurate method that can decide (a) whether a specification of this kind is realizable (i.e., can be simulated by a causal system), and (b) given the action diagrams of the interfaces of two or more communicating systems, whether the systems implementing such independent specifications will correctly interoperate (i.e., satisfy the respective protocols and timing assumptions). First we illustrate the weaknesses of existing action diagram verification techniques: the causality issue is not addressed, and the proposed methods to answer the compatibility (interoperability) question yield false negative answers in many practical situations. We then define the meaning of causality in an action diagram specification and state a set of sufficient conditions for causality to hold. This development then leads to an exact procedure for the verification of the interface compatibility of communicating action diagrams. The results are illustrated on a practical example.

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Section: Resultsmentioning

confidence: 98%

Semantics and verification of action diagrams with linear timing

Khordoc

Cerny

1998

ACM Trans. Des. Autom. Electron. Syst.

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“…See [3] for details about partial and global consistency in CLP (BNR) Prolog. We use a Boolean variable C i,Clk to induce the occurrence of an input event e i ∈ E IN as follows: C i,Clk = (t i < (Clk * P)) and (t i >= (Clk -1)* P).…”

Section: Implementation In Clp(bnr) Prologmentioning

confidence: 99%

“…We must verify the traces over a large enough number of clock cycles k (denoted Maxcycle) within which all events in the TD will have been observed (IN events) and produced (OUT events) by the controller for any possible timing of input events in the TD. Maxcycle can be calculated by the maximum time separation from the origin to the last event in the TD (see e.g., [3] for solution). The set of timed traces TR is thus characterized by a constraint system CS constructed using the above four steps, where k = Maxcycle.…”

Section: The Set Of Timed Traces Trmentioning

confidence: 99%

“…We first calculate Maxcycles using the algorithms in [3] The clause assume_ complement_commit_constraints constructs the complement of the commit constraints and the related assume constraints. The assume constraints A j = (e i , e j , [l ij , u ij ]), j = 1, …, p, are represented as: The complement of a commit constraint C z = (e v , e z , [l vz , u vz ]), z = 1, …, q, are expressed as:…”

Section: Implementation In Clp(bnr) Prologmentioning

confidence: 99%

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Verification of real time controllers against timing diagram specifications using constraint logic programming

Cerny¹,

Jin²

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)

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Given a pseudo-synchronous (sampled input) finite-state machine implementation of a real-time controller (e.g., RTL Verilog code), and a timing diagrams (TDs) specification, the question we wish to answer is whether the controller satisfies this specification. Our method uses Constraint Logic Programming (CLP). The controller FSM is fed with input sequences derived from the assumption constraints on the inputs as stated in the TD, and its outputs are verified against the required timing (commit) constraints in the TD. Our technique considers all input sequences in one consistency check for each commit constraint, carried out on a system of constraints constructed from the TD and the unfolded controller FSM. The number of constraints is linear in the lengths of the intervals of the assumption constraints. The method was implemented in CLP (BNR)Prolog which is based on relational interval arithmetic (RIA). We verified a controller for an asynchronous bus.

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High-level timing analysis using constraint logic programming and interval arithmetic

Girodias¹,

Cerny²

Proceedings 1995 Canadian Conference on Electrical and Computer Engineering

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Solving linear, min and max constraint systems using CLP based on relational interval arithmetic

Cited by 3 publications

References 7 publications

Semantics and verification of action diagrams with linear timing

Semantics and verification of action diagrams with linear timing

Verification of real time controllers against timing diagram specifications using constraint logic programming

High-level timing analysis using constraint logic programming and interval arithmetic

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