Some optimizations of hardware multiplication by constant matrices

Abstract

Abstract-This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.

Towards optimal multiple constant multiplication: A hypergraph approach

“…This has been handled optimally by an exhaustive search of all possible adder interconnections [13], [20]. A third extension is the introduction of delay elements within the multiplier block to form the FIR filter function [9], [25], [28], [38].…”

“…First, the most commonly used is common subexpression sharing/elimination [9], [18], [25], [29], [30], [32]- [34], [36], [38], [42]- [44]. The idea here is to find common patterns in the representation of the multiplier coefficients.…”

“…The problem of multiple constant multiplication (MCM) has been an active research area for a little more than a decade [1]- [5], [9], [10], [14]- [16], [18], [22]- [30], [32]- [34], [36]- [39], [41]- [44]. The MCM problem starts in a number of constant multiplications with the same input.…”

“…However, similar problems has been considered. Algorithms for constant matrix multiplication have been proposed in [9], [16], [33], [34]. This finds applications in linear transforms such as the DCT or FFT [35], and in polyphase FIR filters and filter banks [21].…”

Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space

“…First, the FIR filter is designed in a discrete space such as a finite wordlength space or SPT space to meet a given specification. In the second stage, a common subexpression elimination [1,7,8,18,20,23,24], a graph-based algorithm [2,3,10,21] or a difference algorithm [4,17,22] is applied on the discrete coefficients to find and share the common subexpressions. An obvious disadvantage of such a two-stage optimization is that the search space in the second stage is limited by the finite wordlength or SPT coefficients obtained in the first-stage optimization.…”