Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound

Sampson, Richard J.; Yang, Ming; Wei, Siyuan; Chakrabarti, Chaitali; Wenisch, Thomas F.

doi:10.1109/hpca.2013.6522329

Cited by 46 publications

(43 citation statements)

References 26 publications

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“…This problem is very hard to solve analytically, and more so to solve in a computationally-efficient way, although attempts have been made for 2D imaging [21], [22], [10]. Drastic simplifications have been adopted in the few papers discussing apodization for 3D ultrasound [14].…”

Section: Resultsmentioning

confidence: 99%

Apodization scheme for hardware-efficient beamformer

Ibrahim

Angiolini

Arditi

et al. 2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Abstract-3D ultrasound is an emerging diagnostic technique that extends standard ultrasound imaging by capturing volumes, instead of planes. This brings completely new diagnostic opportunities, among which the possibility of disjoining image acquisition and analysis, thus enabling remote diagnosis, which would bring obvious medical and economic benefits.Unfortunately, 3D ultrasound is several orders of magnitude more computationally complex than 2D imaging. Therefore, algorithmic improvements to simplify the processing are mandatory in order to conceive cheap, portable, low-power imagers.The kernel of the 3D imaging process, called beamforming, consists essentially of computing delay and apodization profiles. We have previously devised an approximation of the delay calculation stage, which dramatically reduces hardware complexity. Unfortunately, this approximation introduces an intrinsic degree of inaccuracy that can be characterized as added image noise.In this paper, we identify an efficient approximated approach to the calculation of apodization profiles, that additionally minimizes (-76%) the error introduced during delay calculation. Together, these two techniques enable an efficient computation of 3D ultrasound images.

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Section: Resultsmentioning

confidence: 99%

Apodization scheme for hardware-efficient beamformer

Ibrahim

Angiolini

Arditi

et al. 2016

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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“…Like most of the standalone accelerators [15][16][17], the accelerator in the proposed system-called reconfigurable application specified processor (RASP), is a loosely coupled configurable engine attached to the AXI bus. Data communication between on-chip memory and external storage, i.e., DDR3 is provided through direct memory access (DMA) in the RASP.…”

Section: System Architecture Overviewmentioning

confidence: 99%

Design and Application Space Exploration of a Domain-Specific Accelerator System

Feng

Wang

et al. 2018

Electronics

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Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision.

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“…Different state-of-the-art systems, either commercial or academic, have only been able to deal with the 3D BF challenge by reducing the number of receive channels, hence simplifying the computation through the usage of far fewer elements, typically 256 or fewer. This can be achieved by using different methods like analog micro-BF [1] or multiplexing [2]. Nonetheless, these systems are still highly complex and expensive.…”

Section: Problem Definition and Previous Workmentioning

confidence: 99%

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer

Simon

Yüzügüler

Ibrahim

et al. 2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beamformer, by proposing a computationally efficient design that is able to perform volumetric real-time beamforming on a single-chip FPGA. The design has been demonstrated for a 32×32-channel receive probe, and we extrapolated the requirements of the architecture for 80×80 channels.I. MOTIVATION Medical ultrasound (US) imaging is well established, being used in a wide range of applications including detecting static structures, such as tumors, and studying dynamic phenomena like blood flow and valve functionality. US imaging is comprises three main processes: insonification, beamforming (BF), and visualization. Insonification is the process of emitting Radio Frequency (RF) acoustic waves from a piezoelectric transducer, called probe, through a body region. The waves are reflected from inhomogeneous tissues interfaces that act as scatterers due to acoustic impedance mismatches. The returned echoes are digitized and processed through an algorithm called Beamforming (BF). Finally, a post-processing step should be performed, including mapping the beamformed signals into screen image pixels.Recently, 3D US imaging has become available. A key advantages is that, since whole volumes are acquired at once, it is possible to remove the traditional dependence on having a trained sonographer operating the probe, in order to locate minute anatomical structures by fine adjustments of the position and orientation of the transducer. This enables telesonography, where even an unskilled operator can upload scans to a hospital where trained radiologists will issue a diagnosis. Unfortunately, present-day 3D imagers are bulky and expensive, suitable only for clinics and hospitals. A portable US platform with cheap, battery-operated electronics would be a breakthrough, enabling telesonography in rescue environments, in rural areas, and in developing countries, with major societal benefits. To this end, we undertake to implement 3D beamforming on a single FPGA. II. PROBLEM DEFINITION AND PREVIOUS WORKBeamforming is the core of any US imaging machine. It is the process of mapping the echoes to their origins by summing them along a certain delay profile, that represents the two-way time-offlight of the acoustic wave from the origin to each scatterer, and back to the all the piezoelectric elements. BF also includes apodization, the weighting of the delayed echoes by a factor that compensates for antenna directivity effects.In volumetric US imaging, a software-based implementation of the beamformer is not optimal if we target a battery-powered platform, whereas a hardware design offers major potential energy savings. One of the critical challenges of 3D US imaging is the number of receiving channels of high-end transducers, up to 100×100 elements, and the correspondingly massive computations required for image reconstruction. Different state-of...

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Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound

Cited by 46 publications

References 26 publications

Apodization scheme for hardware-efficient beamformer

Apodization scheme for hardware-efficient beamformer

Design and Application Space Exploration of a Domain-Specific Accelerator System

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer

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