Sorter Design with Structured Low Power Techniques

Preethi, P.; Mohan, K.; K, Sudeendra Kumar; Mahapatra, Kamalakanta

doi:10.1007/s42979-022-01546-7

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2022

2023

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Cited by 2 publications

References 15 publications

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Optimizing Search and Sort Algorithms: Harnessing Parallel Programming for Efficient Processing of Large Datasets

Maurya,

Sinha,

Suguna

2023

2023 2nd International Conference on Automation, Computing and Renewable Systems (ICACRS)

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Optimizing Search and Sort Algorithms: Harnessing Parallel Programming for Efficient Processing of Large Datasets

Maurya,

Sinha,

Suguna

2023

2023 2nd International Conference on Automation, Computing and Renewable Systems (ICACRS)

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Low-Power Methodologies and Strategies in VLSI Circuits

Preethi

Sapna

Ulla

2022

Advances in Computer and Electrical Engineering

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Due to the fact that low-power gadgets are currently dominating the electronics sectors, researchers are studying their design. Power management is a crucial parameter for designing VLSI circuits since it is essential for estimating the performance of devices, especially those utilized in biomedical and IoT applications. To achieve greater performance, designing a low-power system on a IC is becoming increasingly challenging due to the reduction in size of chip, increases in chip density, and rise in device complexity. Furthermore, for the less than 90 nm node, due to its increasingly complicated design, the total power factor on a chip is turning into a significant difficulty. Leakage current also has a significant effect on how low-power VLSI devices manage their power. Leakage and dynamic power reduction are increasingly being prioritized in VLSI circuit design in order to improve the battery life of electronic portable devices. The many methodologies, tactics, and power management schemes that can be employed for the design of low-power circuit systems are discussed in this chapter.

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Sorter Design with Structured Low Power Techniques

Cited by 2 publications

References 15 publications

Optimizing Search and Sort Algorithms: Harnessing Parallel Programming for Efficient Processing of Large Datasets

Optimizing Search and Sort Algorithms: Harnessing Parallel Programming for Efficient Processing of Large Datasets

Low-Power Methodologies and Strategies in VLSI Circuits

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