SOT-MRAM Based Main Memory: An Alternative to DRAM

Rai, Sadhana; Kallinatha, H D; Talawar, Basavaraj

doi:10.1109/conecct55679.2022.9865703

Cited by 1 publication

(2 citation statements)

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“…Focusing on the circuit-level analysis of 1GB to 128GB main memory. The ensuing analysis is conducted based on our in-depth understanding and by compelling evidence from [6] and [38].…”

Section: A Analysis Of Micro-architecture Level Nvm Main Memory Desig...mentioning

confidence: 99%

“…The potential of SOT-MRAM as a lowpower, high-speed spintronic device for on-chip memory and main memory in HPC and AI applications is highlighted by Zheng et al [5]. The behaviour of SOT-MRAM in embedded systems was analyzed in [6] with experiments, showing an average reduction in power by 47.1% and a performance increase of 39.9% than DRAM. Reliable evaluation of SOT-MRAM-based main memory is challenging due to the public unavailability of parameters related to timing and current.…”

Section: Introductionmentioning

confidence: 99%

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A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

Kallinatha,

Rai,

Talawar

2024

IEEE Access

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Alternative memory technologies must be explored to foster the need for modern applications. This work proposes a novel approach incorporating Spin-Orbit-Torque-Magnetic-RAM (SOT-MRAM) into hybrid and full main memory architectures within a multi-core system, encompassing various memory configurations and capacities. The study addresses the challenge of evaluating SOT-MRAM-based memory systems when specific SOT-MRAM memory parameters are not publicly available. The research methodology encompasses micro-architectural (circuit-level) design space exploration and comprehensive full system simulations, which evaluate benchmark programs representing diverse application domains. The evaluation includes three memory structures with varying memory organizations and capacities. The results underscore SOT-MRAM as a robust replacement for DRAM or hybrid memory, offering compelling advantages such as a remarkable 74.05% reduction in power consumption, a noteworthy 40.10% increase in bandwidth utilization, and a significant 72.85% reduction in Energy-Delay Product (EDP). Additionally, the incurred maximum latency penalties are minimal, with a 3.71% increase for hybrid structures and a mere 0.07% for standalone SOT-MRAM memory structures.

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“…Focusing on the circuit-level analysis of 1GB to 128GB main memory. The ensuing analysis is conducted based on our in-depth understanding and by compelling evidence from [6] and [38].…”

Section: A Analysis Of Micro-architecture Level Nvm Main Memory Desig...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%