Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Yoon, Jun-Sik; Lee, Seung-hwan; Lee, Junjong; Jeong, Jinsu; Yun, Hyeok; Kang, Bohyeon; Baek, Rock‐Hyun

doi:10.1109/access.2019.2956503

Cited by 15 publications

(5 citation statements)

References 19 publications

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“…Some parameters related to surface roughness scatterings were also modified to fit the I ds in the strong inversion region accordingly. These calibration flows were equivalent as in [26]. After calibration, FinFETs were scaled down to the 3-nm node for comparison with GAAFETs.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Yoon¹,

Jeong²,

Lee³

et al. 2021

Nanowires - Recent Progress

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“…Both devices share the physical parameters fullycalibrated by fitting I-V curves of 10-nm silicon FinFETs [3] as presented in a previous paper [29]. By adapting identical physical parameters, characteristics of FinFETs and NSFETs are compared fairly.…”

Section: Simulation Structures and Methodologymentioning

confidence: 99%

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

2021

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Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress (SZZ) predominantly causes variations of on-state current (ΔIon). NSFETs exhibit the greater ΔIon than FinFETs because electron velocities and densities in channels vary with respect to SZZ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents (Icap, Ib-b). NSFETs exhibit the greater |Icap|/Ion than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the |Ib-b|/Ion is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases |Ib-b|/Ion only, but short rise time of TSV signals increases both |Icap|/Ion and |Ib-b|/Ion. Unfortunately, conventional devices cannot satisfy criterion for analog applications (|Icap, Ib-b|/Ion< 0.5%); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The |Icap|/Ion for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The |Ib-b|/Ion for NSFETs decreases remarkably due to completely blocked Ib-b path, but FinFETs still have Ib-b path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.

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“…For accurate simulation, mixed-mode simulation was conducted to consider both front-end-of-line (FEOL) and back-end-of-line (BEOL) [11]. All TCAD simulation models for the FEOL region were used as described in [3]. The bottom-tier device was fully calibrated to an Intel 10nm node device [12].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

“…However, it is difficult to scale the contact-poly-pitch (CPP) to less than 42 nm [2] due to the device performance degradation by the short channel effect despite having excellent gate controllability. Therefore, various studies such as source/drain patterning (SDP), buried power rail (BPR), complementary FET (CFET), and monolithic 3D (M3D), which can reduce the cell area in different ways without scaling the device itself, are being conducted [3][4][5][6]. Among them, M3D and CFET are promising with high area scaling by stacking devices, and in particular, M3D has the advantage of less difficulty in device processing than CFET.…”

Section: Introductionmentioning

confidence: 99%

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

et al. 2021

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For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM3D). SRAM3D could not directly connect the top-tier device and the bottom-tier metal line. Thus two tiers had to be connected by bypassing the metal line. As a result, SRAM3D wasted the area to place the monolithic interlayer via and did not get 50 % area scaling. However, gate and S/D bottom contact schemes, GBC and SDBC, could solve these problems. Although these methods required additional process steps, they brought significant advantages in interconnect RC and PPA. Based on a 26 nm width nanosheet transistor, SRAM3D showed a 30 % area reduction compared to 2D SRAM (SRAM2D), whereas SRAMSDGBC showed a 50 % area reduction. In the ideal (worst) case which ignoring (considering) the array resistance, the read and write access time of SRAMSDGBC were improved 7.7 % (19 %) and 8.3 % (33 %) than SRAM3D, and the write dynamic power was improved by 5.9 % (5 %). Especially, SRAMSDGBC showed improved PPA in the worst case compared to SRAM2D_Cu, which had relatively small interconnect resistivity. Namely, GBC and SDBC schemes are essential to enhance the PPA of M3D cells and will be a promising scheme in M3D SRAM and other logic cells.

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Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Cited by 15 publications

References 19 publications

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Gate-All-Around FETs: Nanowire and Nanosheet Structure

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes

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