Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI

Harden, Jane; Mangir, Tulin

doi:10.1109/proc.1984.12917

Cited by 68 publications

(17 citation statements)

References 81 publications

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“…In Mangir (1984) these and other fault mechanisms are discussed. For fielded devices the important mechanisms (not discussed above) include random changes of state due to exposure to alpha particles and other ionizing radiation, shorts between metalizations d.ie to oxide breakdown from static discharges, transistor threshold shifts due to hot electrons, shorts between diffusion regions due to charge spreading, and line coupling and charge loss (memory devices) due to degradation of insulator quality from extended use.…”

Section: Physical Fault Mechanisms In Vlsi Devicesmentioning

confidence: 99%

“…Recent descriptions of failure mechanisms are given in Mangir (1984), Wadsack (1978), Maly (1987), Ghate (1982), Green (1987 and, and Green and Denson (1988 Electromigration is another defect mechanism that can arise during field operation (Ghate, 1982;Ho, 1982). Electromigration is the transport of metal due to an impressed DC electric field.…”

Section: Physical Fault Mechanisms In Vlsi Devicesmentioning

confidence: 99%

“…However, it is widely known that the single stuck-at fault model falls short of characterizing all faults (Mangir, 1984;Abraham and Fuchs, 1986;Galiay et al 1980;Maly, 1987;Cunningham et al 1987;Breuer et al 1983a;Fujiwara, 1985). Furthermore, not all s/a faults at the gate level can physically occur (Maly, 1987).…”

Section: -6mentioning

confidence: 99%

“…Unfortunately, there are many faults that can not be generically described at the gate-level. These are mostly caused by shorts that change the desired function of a gate, or can cause a change in the function of a group of gates (Cunningham et al, 1987;Galiay et al, 1980;Mangir, 1984). Since the effect of faults depends on the layout of the device and the specific gate topology, it is difficult to decompose these faults any further (except for the wired-logic behavior described above).…”

Section: -6mentioning

confidence: 99%

See 3 more Smart Citations

Analysis and Demonstration of Diagnostic Performance in Modern Electronic Systems

Weiss¹,

Deckert²,

Kelly³

1991

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Section: Physical Fault Mechanisms In Vlsi Devicesmentioning

confidence: 99%

Section: Physical Fault Mechanisms In Vlsi Devicesmentioning

confidence: 99%

Section: -6mentioning

confidence: 99%

Section: -6mentioning

confidence: 99%

See 2 more Smart Citations

Analysis and Demonstration of Diagnostic Performance in Modern Electronic Systems

Weiss¹,

Deckert²,

Kelly³

1991

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“…Most of the defects and failures in present day integrated circuits can be abstracted to shorts and opens in the interconnects and degradation of devices [4]. Transistor level shorts and opens model many of the physical failures and defects in ICs [5].…”

Section: Introductionmentioning

confidence: 99%

Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits

Menon

Jayasumana

Malaiya

Proceedings of the Sixth Great Lakes Symposium on VLSI

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Ab st rac tCombining the advantages of Bipolar and CMOS, BiC-MOS is emerging as a major technology for high speed, high performance, digital and mixed signal applications. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. This paper presents effects of bridging faults affecting p-or n-parts and input bridging faults of logical nodes affecting p-and n-parts. It is shown that bridging faults can be detected by I D D Q monitoring in BiCMOS devices. An input pattern classification scheme is presented for bridging faults. These classes of input patterns are then used to obtain test sets for bridging fault detection.

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A two‐step methodology for CMOS VLSI reliability improvement: Step one

Davies

Miles

Postoyalko

1988

Quality & Reliability Eng

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Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck‐at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two‐step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre‐SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.

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Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI

Cited by 68 publications

References 81 publications

Analysis and Demonstration of Diagnostic Performance in Modern Electronic Systems

Analysis and Demonstration of Diagnostic Performance in Modern Electronic Systems

Input pattern classification for transistor level testing of bridging faults in BiCMOS circuits

A two‐step methodology for CMOS VLSI reliability improvement: Step one

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