SP: an advanced surface-potential-based compact MOSFET model

Gildenblat, G.; Wang, Hailin; Chen, Ten-Lon; Gu, Xiaoxiong; Cai, X.

doi:10.1109/jssc.2004.831604

Cited by 118 publications

(59 citation statements)

References 48 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the SP [26,6] and PSP [7] models, the drain current and the intrinsic terminal charges are formulated using the symmetric linearization method. The inversion charge (per unit area) is approximated by its first-order Taylor expansion at the potential middle point w sm :…”

Section: Symmetrically Linearized Charge-sheet Model For Dd-soi Mosfetsmentioning

confidence: 99%

“…This results in unit value of the linearization coefficient. 1 Hence the original symmetric linearization method [6,7] cannot be applied directly to the modeling of dynamically depleted SOI MOSFETs.…”

Section: Symmetrically Linearized Charge-sheet Model For Dd-soi Mosfetsmentioning

confidence: 99%

“…The surface-potential-based approach, which has emerged as the mainstream of the compact modeling for both bulk [6,7] and PD-SOI [8,9] devices, has been already introduced for the DD-SOI in [3,[10][11][12]. It starts from the first integral of Poisson's equation in the channel region.…”

Section: Introductionmentioning

confidence: 99%

“…To obtain the final form of SPE, we follow the SP and PSP models development [6,9,7,19] and note that it is desirable to have…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

Yao

Gildenblat

2010

Solid-State Electronics

View full text Add to dashboard Cite

Section: Symmetrically Linearized Charge-sheet Model For Dd-soi Mosfetsmentioning

confidence: 99%

Section: Symmetrically Linearized Charge-sheet Model For Dd-soi Mosfetsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…To obtain the final form of SPE, we follow the SP and PSP models development [6,9,7,19] and note that it is desirable to have…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

Yao

Gildenblat

2010

Solid-State Electronics

View full text Add to dashboard Cite

“…Since the ability to modify a silicon process as desired for 77 K CMOS operation was not available, these modifications were done synthetically beginning with the "base" 300 K model; suitable descriptions of the desired 77 K CMOS technology were thus created. Please note that modernized MOS transistor model forms [16] are required for the use of modern circuit design techniques. Figure 2 compares the turn-on characteristics of a 0.18 µm nMOS device at 300 K and at 77 K, when in the latter case the device has simply been "dunked" in liquid nitrogen.…”

Section: Technologymentioning

confidence: 99%

An evaluation of deep-submicron CMOS design optimized for operation at 77 K

Foty¹

2006

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Using a careful and insightful analysis of the possible benefits of 77 K CMOS in submicron technology from a decade ago [1], the development of 77 K CMOS in presentday deep submicron technology is evaluated. It is found that the basic principles from the earlier study-that the real benefit of 77 K CMOS operation is the ability to provide "pure" scaling of the threshold voltage and thus to allow aggressive super-scaling of MOS transistor dimensions-not only holds in present-day CMOS processes, but is even more important in that regard. A detailed analysis of CMOS technology, digital circuit behavior, and analog circuit behavior is provided. It is noted that not only does properly-designed 77 K CMOS technology provide opportunities; it also addresses some of the most fundamental difficulties facing CMOS technology and CMOS circuit design.

show abstract

RF MOSFETs

Kumari,

Gupta,

Saxena

2024

Encyclopedia of RF and Microwave Engineering

View full text Add to dashboard Cite

In this article, the RF performance of different MOSFET architectures such as Silicon‐On‐Insulator (SOI), Lightly Doped Drain (LDD) MOSFET, Graphene FET, and Negative Capacitance (NC) FET have been reported based on the previously reported work in the form of equivalent circuits. Using the data reported in the literature, the cutoff frequency and maximum frequency of oscillation have been summarized with varying channel lengths. Compared results show that multigate architecture results in higher cutoff frequency and a maximum frequency of oscillation, which can be further increased by decreasing the channel length of the MOSFET architecture. However, the deterioration in the resulting device gain at lower channel length has also been reported. Furthermore, the performance of SOI, Silicon‐on‐Nothing (SON), Double Gate (DG), Double‐Gate Silicon‐On‐Insulator (DGSOI), and Empty Space in Double‐Gate (ESDG) architectures have been explored using ATLAS TCAD software tool for RF and digital parameters investigation. The various parameters explored in this article are current density, electric field, breakdown voltage, impact ionization rate, scattering parameters, noise conductance, minimum noise figure, and cross‐correlation factor. The presented results show that, for the same drain current value, ESDG architecture has higher device gain compared to other devices used for comparison along with higher cutoff frequency. However, this higher device gain comes at the cost of a slightly higher minimum noise figure but with improved noise conductance and cross‐correlation factor (slightly higher than DG). Thus, ESDG is a reliable candidate for LNA design compared to other devices.

show abstract

SP: an advanced surface-potential-based compact MOSFET model

Cited by 118 publications

References 48 publications

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs

An evaluation of deep-submicron CMOS design optimized for operation at 77 K

RF MOSFETs

Contact Info

Product

Resources

About