Space charge capacitance study of GaP/Si multilayer structures grown by plasma deposition

Abstract

Microcrystalline GaP/Si multilayer structures grown on GaP substrates using combination of PE-ALD for GaP and PECVD for Si layers deposition are studied by three main space charge capacitance techniques: C-V profiling, admittance spectroscopy (AS) and deep level transient spectroscopy (DLTS), which have been used on Schottky barriers formed on the GaP/Si multilayer structures. C-V profiling qualitatively demonstrates an electron accumulation in the Si/GaP wells. However, quantitative determination of the concentration and spatial position of its maximum is limited by the strong frequency dependence of the capacitance caused by electron capture/emission processes in/from the Si/GaP wells. These processes lead to signatures in AS and DLTS with activation energies equal to 0.39±0.05 eV and 0.28±0.05 eV, respectively, that are linked to the energy barrier at the GaP/Si interface. It is shown that the value obtained by AS (0.39±0.05 eV) is related to the response from Si/GaP wells located in the quasi-neutral region of the Schottky barrier, and it corresponds to the conduction band offset at the GaP/Si interface, while DLTS rather probes wells located in the space charge region closer to the Schottky interface where the internal electric field yields to a lowering of the effective barrier in the Si/GaP wells. Two additional signatures were detected by DLTS, which are identified as defect levels in GaP. The first one is associated to the SiGa+VP complex, while the second was already detected in single microcrystalline GaP layers grown by PE-ALD.

Carrier density distribution in AlGaAs/GaAs superlattices with different numbers of quantum wells determined by capacitance-voltage profiling

“…Therefore, one of the most promising methods for determining the concentration profile of free charge carriers is the method of capacitance-voltage (or C-V) profiling [9]. It is successfully used to observe the distribution of carriers in semiconductor low-dimensional structures [10][11][12], including superlattices [13].…”