Space Vector Techniques for a Binary-Cascaded Multilevel Inverter Operating Under Reduced Common-Mode Voltage With Reduced Commutations

Abstract

This paper presents a novel space vector pulse width modulation (SVPWM) for a three-phase binary cascaded multilevel inverter. The SVPWM could become impractical in multilevel inverters (MLIs) because of its increasing complexity with a larger number of levels. The gh coordinate system can ease the digital implementation, but to generate the inverter's abc states from the nearest three vectors (NTVs), iterative computations are required every sampling instant. This paper proposes further reduction of computations by directly generating the abc state with minimum common-mode voltage (CMV) from a gh vector. Subsequently, only one vector among the NTVs is required for implementing the proposed SVPWM. The reduced CMV profile within the NTVs further permits the reduction of commutations by clamping one phase during a sampling period. The presented technique exhibits full dc bus utilization capability and can be implemented in the binary cascaded MLI (BCMLI) and further applied to any M-level MLI. Also, if M is considerably large or if switching losses and electromagnetic interference emissions must be minimized, nearest vector modulation with reduced CMV along with line-frequency operation of high-voltage cells can be implemented to reduce the switching losses. Experiment results of a BCMLI is presented to verify the effectiveness of the proposed technique.INDEX TERMS Common-mode voltage (CMV), multilevel inverter (MLI), nearest vector modulation (NVM), space vector pulse width modulation (SVPWM), switching loss reduction.

Cascaded Multilevel Structure With Three-Phase and Single-Phase H-Bridges for Open-End Winding Induction Motor Drive

“…To see that the open-end winding proposed topologies, namely the S-T configuration, allow using a lower minimum level of the inverters DC voltage source, a comparison to the classical cascaded H-bridge multilevel topology is done [15]. For the H-bridge topology, the minimum level of the inverters DC voltage source can be determined by (13).…”

“…Due to the above advantages many multilevel topologies have been developed and implemented in VSI drives. The most known, studied and used are the neutral-point-clamped (NPC), the flying capacitor, cascaded H-bridge topologies, and T-Type [12][13][14][15][16][17][18]. The first two topologies need to balance the capacitors voltages, requiring more elaborated control systems [19][20][21][22].…”