Spare block cache (SprBlk): Fault resilience and reliability at low voltages

Siddique, Nafiul Alam; Badawy, Abdel-Hameed A.

doi:10.1109/uic-atc.2017.8397619

Cited by 3 publications

(2 citation statements)

References 17 publications

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“…For another approach for low V cc operations in caches or SRAM arrays, the spare blocks [39] (i.e., redundancy-based scheme) are used to replace the faulty cache blocks to enable reliable cache operations under ultra-low V cc . ZCAL cache [40] was also proposed to prevent access time failureinduced malfunction caused by ultra-low voltage operations.…”

Section: Related Workmentioning

confidence: 99%

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Kong

Hur

2020

IEEE Access

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Near-threshold computing (NTC) has recently emerged and been considered as a strong candidate for future energy-efficient computing. However, adverse impacts from process variation such as delay and power fluctuations within die as well as across dies are much more severe than the super-threshold regime. In particular, static random access memory (SRAM)-based components (e.g., cache memories) are easily affected by process variation in NTC, resulting in large delay fluctuations. It incurs a huge loss in the maximum clock frequencies of processors, which eventually leads to huge yield losses. In this paper, we first analyze L1 data cache yield in NTC and reveal an inefficiency of frequency binning for yield improvement in NTC. We then introduce a variable latency L1 data cache for NTC to obtain a sufficient yield. By allowing the higher cache access cycles, we can improve cache yield with only a little performance overhead. Moreover, we propose an adaptive line migration technique which improves performance and energy efficiency of variable latency caches. The cache line which is expected to be frequently accessed in the near future is dynamically migrated to the fastest way in a cache set. According to our evaluation, our cache architecture greatly improves cache yield with only a little performance, energy, and area overhead.

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Section: Related Workmentioning

confidence: 99%

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Kong

Hur

2020

IEEE Access

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“…Not surprisingly, excessive cache capacity can be wasted in these schemes. Siddique and Badawy [15] presented a novel cache architecture that uses spare subblocks as back up sub-blocks in a set associative cache. However, the number of redundancy sub-blocks in a cache set is fixed, which is not flexible enough for different scenarios.…”

Section: B the Cache Architecturementioning

confidence: 99%

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

et al. 2019

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The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the potential timing failures. Unfortunately, the performance benefit brought by this speculative scheme might be nullified by the extra cycles used to correct the errors. Therefore, in a cache architecture, cachelines containing bit cells with timing failure bring significant performance degradation in a low-voltage scenario. In this paper, we propose the set-associative L1 and L2 Remapping and Reuse-aware timing Speculation caches (RRS caches) based on the cross-sensing SSRAM to reduce the weak cacheline access penalties under low supply voltages. RRS caches improve the proportion of the error-free cachelines (or strong cachelines) by clustering as more as possible bit cells with timing failures into weak cachelines. In addition, RRS caches swap the frequently reused data to the error-free cachelines to further reduce the average access latency and the energy consumption by an optimized filling/replacement policy. We compared the performance, energy consumption and area overhead of RRS caches with those of state-of-the-art approaches. According to our simulation results, RRS caches improve the system performance close to that of the Perfect caches in a four-core processor with only 0.12% extra energy consumption, 4.12% extra area overhead in the L1 cache and 2.69% extra energy consumption, 5.66% extra area overhead in the L2 cache compared to the cache designs with the raw SSRAM. INDEX TERMS Cacheline remapping, low-voltage cache, near-threshold voltage, replacement policy, timing speculation SRAM.

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SprBlk cache

Siddique

Badawy

2017

Proceedings of the International Symposium on Memory Systems

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Spare block cache (SprBlk): Fault resilience and reliability at low voltages

Cited by 3 publications

References 17 publications

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

SprBlk cache

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