SPC05-3: On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference

Müller, Olivier; Baghdadi, Amer; Jézéquel, Michel

doi:10.1109/glocom.2006.558

Cited by 5 publications

(3 citation statements)

References 15 publications

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“…As presented in [15], implementing an efficient turbodecoder requires a good exploitation of the parallelism. In turbo decoding with the BCJR algorithm, parallelism techniques can be classified at three levels: (1) BCJR metric level parallelism, (2) BCJR SISO decoder level parallelism, and (3) Turbo-decoder level parallelism.…”

Section: Convolutional Turbo Decodingmentioning

confidence: 99%

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding

Müller

Baghdadi

Jézéquel

2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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Section: Convolutional Turbo Decodingmentioning

confidence: 99%

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding

Müller

Baghdadi

Jézéquel

2008

2008 the 19th IEEE/IFIP International Symposium on Rapid System Prototyping

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“…State-of-the-art research is mainly focused on parallel processing of frame subblocks and on the parallel processing issues, such as computation complexity [3,5], memory saving [3,5,6], initializations [5,7], or on-chip communication requirements [8,9]. Recently, a new parallelism technique named shuffled decoding was introduced to process in parallel the component decoders [10,11]. However, interactions between these diverse parallelism techniques and different granularity levels are rarely discussed.…”

Section: Introductionmentioning

confidence: 99%

Parallelism Efficiency in Convolutional Turbo Decoding

Müller

Baghdadi

Jézéquel

2010

EURASIP J. Adv. Signal Process.

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Parallel turbo decoding is becoming mandatory in order to achieve high throughput and to reduce latency, both crucial in emerging digital communication applications. This paper explores and analyzes parallelism techniques in convolutional turbo decoding with the BCJR algorithm. A three-level structured classification of parallelism techniques is proposed and discussed: BCJR metric level parallelism, BCJR-SISO decoder level parallelism, and Turbo-decoder level parallelism. The second level of this classification is thoroughly analyzed on the basis of parallelism efficiency criteria, since it offers the best tradeoff between achievable parallelism degree and area overhead. At this level, and for subblock parallelism, we illustrate how subblock initializations are more efficient with the message passing technique than with the acquisition approach. Besides, subblock parallelism becomes quite inefficient for high subblock parallelism degree. Conversely, component-decoder parallelism efficiency increases with subblock parallelism degree. This efficiency, moreover, depends on BCJR computation schemes and on propagation time. We show that componentdecoder parallelism using shuffled decoding enables to maximize architecture efficiency and, hence, is well suited for hardware implementation of high throughput turbo decoder.

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“…This is due to the decoding process because no extrinsic information is available at the first iteration. It is possible to implement a shuffled iterative decoding [21,22] in order to achieve the same performance as for the classical turbo encoder and avoid adding iterations in practice. In shuffled decoding, the decoder updates the extrinsic information as soon as possible, without waiting for all the copies of a given data to be processed.…”

Section: Another Representation Of Turbo Codesmentioning

confidence: 99%

A survey of three-dimensional turbo codes and recent performance enhancements

Ismail

Douillard

Kerouedan

2013

J Wireless Com Network

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This paper presents a survey of two techniques intended for improving the performance of conventional turbo codes (TCs). The first part of this work is dedicated to explore a hybrid concatenation structure combining both parallel and serial concatenation based on a three-dimensional (3D) code. The 3D structure, recently introduced by Berrou et al., is able to ensure large asymptotic gains at very low error rates at the expense of an increase in complexity and a loss in the convergence threshold. In order to reduce the loss in the convergence threshold, the authors consider first a time-varying construction of the post-encoded parity. Then, they investigate the association of the 3D TC with high-order modulations according to the bit-interleaved coded modulation approach. The second part of this study deals with irregular TCs. In contrast to 3D TCs, although irregular TCs can achieve performance closer to capacity, their asymptotic performance is very poor. Therefore, the authors propose irregular turbo coding schemes with suitable interleavers in order to improve their distance properties. Finally, a modified encoding procedure, inspired from the 3D TC, makes it possible to obtain irregular TCs which perform better than the corresponding regular codes in both the waterfall and the error floor regions.

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SPC05-3: On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference

Cited by 5 publications

References 15 publications

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding

From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding

Parallelism Efficiency in Convolutional Turbo Decoding

A survey of three-dimensional turbo codes and recent performance enhancements

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