Specification and verification of security in reconfigurable scan networks

Deng

et al. 2019

Sensors

Wireless sensor networks (WSN) have deeply influenced the working and living styles of human beings. Information security and privacy for WSN is particularly crucial. Cryptographic algorithms are extensively exploited in WSN applications to ensure the security. They are usually implemented in specific chips to achieve high data throughout with less computational resources. Cryptographic hardware should be rigidly tested to guarantee the correctness of encryption operation. Scan design improves significantly the test quality of chips and thus is widely used in semiconductor industry. Nevertheless, scan design provides a backdoor for attackers to deduce the cipher key of a cryptographic core. To protect the security of the cryptographic system we first present a secure scan architecture, in which an automatic test control circuitry is inserted to isolate the cipher key in test mode and clear the sensitive information at mode switching. Then, the weaknesses of this architecture are analyzed and an enhanced scheme using concept of test authorization is proposed. If the correct authorization key is applied within the specific time, the normal test can be performed. Otherwise, only secure scan test can be performed. The enhanced scan scheme ensures the security of cryptographic chips while remaining the advantages of scan design.

“…Secure techniques based on restricted access to scan chains are proposed in [31,32,33]. The scheme proposed in [31] inhibits the normal scan operation if the user is unauthorized.…”

Section: Scan Design and Countermeasures Thwarting Scan Attacksmentioning

confidence: 99%

Section: Scan Design and Countermeasures Thwarting Scan Attacksmentioning

confidence: 99%

Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications

Deng

et al. 2019

Sensors

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

“…[21], [23], [25], [28], [29]) are focusing on the integrity attribute, mostly addressing HW trojan detection . There also exist some works that additionally target ( [19], [20], [22], [24], [30]) or are exclusively considering ( [26], [27]) the confidentiality aspect.…”

Section: A Security Aspectsmentioning

confidence: 99%

“…Several solutions in security verification are restricted to target specific architectures or types of modules such as Reconfigurable Scan Networks (RSNs) [22], [26] or macroasynchronous micro-synchronous pipelines [29].…”

Section: A Security Aspectsmentioning

confidence: 99%

Towards Multidimensional Verification: Where Functional Meets Non-Functional

Jenihhin

Lai

Ghasempouri

et al. 2018

Trends in advanced electronic systems' design have a notable impact on design verification technologies. The recent paradigms of Internet-of-Things (IoT) and Cyber-Physical Systems (CPS) assume devices immersed in physical environments, significantly constrained in resources and expected to provide levels of security, privacy, reliability, performance and low power features. In recent years, numerous extra-functional aspects of electronic systems were brought to the front and imply verification of hardware design models in multidimensional space along with the functional concerns of the target system. However, different from the software domain such a holistic approach remains underdeveloped. The contributions of this paper are a taxonomy for multidimensional hardware verification aspects, a state-of-the-art survey of related research works and trends towards the multidimensional verification concept. The concept is motivated by an example for the functional and power verification dimensions.

“…IEEE P1687 标准 [1] 也被称为内部联合测试行动组(internal joint test action group, IJTAG), 使用段插入位(segment insert bit, SIB)构建可重构扫描网络, 通过向 SIB 移入配置数据改变扫描链. 虽然在可重构扫描网络中可以灵活地配置扫描路径, 但是也存在着一些安全问题 [2][3] [4][5][6][7][8][9][10][11][12] ; 另一类是防止恶意仪器对传输数据的窜改和嗅探攻击 [13][14][15][16] . 文献 [4][5] 通过使用多个分布式密钥位增大未经授权用户对重要仪器访问的难度.…”

unclassified

Lock Isolation Security Architecture for Reconfigurable Scanning Networks

Liu

J Comput-Aided Design Comput Graphics

Ren

2021

To protect the reconfigurable scanning network from the influence of unauthorized access, tampering of transmitted data by malicious instruments and sniffing, a lock isolation security structure is proposed. Firstly, the presented structure divides the instruments without security threat to each other into one group, and the groups can be accessed one by one via the isolated signals, which can prevent malicious instruments tampering and sniffing transmitted data. Secondly, the key instruments are protected by the lock segment insertion bit. The lock segment insertion bit can only be opened when multiple key values at specific positions are set to specific values (0, 1 sequence), which can increase the difficulty of unauthorized access. Besides, to reduce the hardware overhead, and the difficulty of place and route caused by excessive instrument groups, instrument grouping algorithm is proposed. The proposed algorithm firstly constructs an undirected graph based on the security relationship among instruments. Then the maximal independent sets of the undirected are obtained. In this way, the number of instrument groups is reduced greatly. Compared to other similar methodologies, the experimental results conducted on ITC 02 benchmark circuits show that the time consumption for opening the locking segment insertion bit of the proposed security structure increased by 7 times, and the average percentage reduction of area, power consumption and wire length is 3.81%, 9.02% and 4.55%, respectively.