2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) 2011
DOI: 10.1109/apec.2011.5744741
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Specifications-driven design space boundaries for Point-of-Load converters

Abstract: This paper derives physical constraints for the output filter of a Point-of-Load (POL) converter. Time-optimal control theory is employed to translate the POL static and dynamic specifications into boundaries in the L-C design space, ultimately defining a set Σ of L and C values compatible with the application requirements. Outside the identified set Σ, no controller is capable of meeting the POL specifications; inside the identified set Σ, various degrees of approximation of the time-optimal response are poss… Show more

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Cited by 9 publications
(9 citation statements)
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“…This integral gain K i must be limited in order for a single unit impulse of the error signal to produce a step change in the controlled quantity (e.g., output voltage). This condition is expressed in Equation (23). Theoretically, the parameter a is equal to 1, but in practice a, safety factor is considered, which can typically be a = 0.5.…”
Section: Limit Cycling Conditionsmentioning
confidence: 99%
“…This integral gain K i must be limited in order for a single unit impulse of the error signal to produce a step change in the controlled quantity (e.g., output voltage). This condition is expressed in Equation (23). Theoretically, the parameter a is equal to 1, but in practice a, safety factor is considered, which can typically be a = 0.5.…”
Section: Limit Cycling Conditionsmentioning
confidence: 99%
“…This converter could be used as the niBP of the DC-PDS. The limits Δv op and Δv ot imposed on the output voltage by the power quality requirements set a lower bound for the buck output capacitor C. These minimum values C(Δv op ), that guarantees a maximum steady state Δv op , and C(Δv ot ), which ensures a maximum Δv ot during a load step of magnitude ΔI o , can be calculated as in [14], [15].…”
Section: Converter Design Requirements In a Dc-pdsmentioning
confidence: 99%
“…In a synchronous buck converter, power losses are mainly due to the pair of MOSFETs and the inductor. The current ripple through the capacitors is commonly small enough to consider their losses negligible [15], although it is also relatively easy to model if the capacitor series resistance and the current flowing through them is known.…”
Section: Converter Design Requirements In a Dc-pdsmentioning
confidence: 99%
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