Speculative Dataflow Circuits

Abstract

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract parallelism in irregular and control-dominated applications, dynamic scheduling opens a door to speculative execution, one of the most powerful ideas in computer architecture. Speculation allows executing certain operations before it is known whether they are correct or required: it can significantly increase fine-grain parallelism in loops where the condition takes many cycles to compute; it can also increase the performance of circuits limited by potential dependencies by assuming independence early on and by reverting to the correct execution if the prediction was wrong. In this work, we detail our methodology to enable tentative and reversible execution in dynamically scheduled dataflow circuits. We create a generic framework for handling speculation in dataflow circuits and show that our approach can achieve significant performance improvements over traditional circuit generation techniques.

Buffer Placement and Sizing for High-Performance Dataflow Circuits

“…We compare our optimization approach with a naive buffer placement strategy, discuss the runtime of our algorithm and methods to improve it, and investigate the effectiveness of the period constraint. Recent papers have directly compared dataflow circuits to commercial statically-scheduled HLS results [15,16] and this comparison is, therefore, outside of the scope of this paper.…”

Toward Speculative Loop Pipelining for High-Level Synthesis

“…Existing work on speculative execution for HLS either addresses the problem of runtime data-dependence management [6], [7], or improve tool support for loops with complex control-flow [8]- [13]. The only exception is the work by Josipović et al [14] that adds speculation to dataflow circuits and is capable of addressing both issues. We discuss related work further in Section VI.…”

“…We propose to express SLP directly at the sourcelevel, in contrast to prior work [7], [14] that operates at the HLS back-end or at the RTL-level. Our insight consists in decoupling the pipeline control logic from the pipelined datapath in the source code.…”

“…Because they are not amenable to static analysis, these patterns limit the ability to statically pipeline the loop. Prior work has addressed this limitation through memory speculation: speculate that the dependence distances are sufficiently large to overlap consecutive iterations [6], [7], [12]- [14]. These approaches use runtime checks to determine the actual dependence distance to detect and to recover from memory dependence hazards.…”

“…This benchmark aims at demonstrating that our approach can automatically infer an in-order pipelined micro-architecture (with its corresponding hazard detection logic) directly from an ISS specification. • Newton-Raphson: A root-finding algorithm, which was used by Josipović et al in their work on speculative dataflow circuits [14]. We used the code made available 2 by the authors.…”