Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

Angeline, A. Anita; Bhaaskaran, V. S. Kanchana

doi:10.1080/00207217.2020.1726486

Cited by 12 publications

(2 citation statements)

References 18 publications

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“…The aspect ratios of the precharging device and the serially connected device are put equal to 10. Since both the precharging time and the average power consumption are dependent on the input pattern, half of the input bits is assumed to be at logic “1” and the other half is assumed to be at logic “0.” Although both the power consumption and the PDP of the scheme of Angeline and Bhaaskaran 47 are smaller than those of the proposed scheme, it must be noted that the load capacitance of this scheme is just the parasitic capacitance at the gate terminal of the keeper. Other schemes for comparison can be found in other studies 48–55 …”

Section: Simulation Results Discussion and Comparisonsmentioning

confidence: 90%

Proposed time‐mode wide fan‐in NAND and NOR gates

Sharroush

Badry

2023

Circuit Theory & Apps

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Summary CMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades. This is the case especially with scaling down the power‐supply voltage associated with technology scaling. In this paper, a time‐mode scheme that utilizes a floating‐gate MOSFET (FGMOS) transistor is proposed. The proposed scheme showed good performance for wide fan‐in NAND and NOR gates. The design issues of the proposed scheme like the speed and the power consumption are investigated quantitatively. The performance of the proposed scheme is confirmed through simulation using the 45‐nm CMOS predictive technology model (PTM) with a 1‐V power‐supply voltage. 64‐input NAND and NOR gates realized using this scheme have time delays of 0.375 and 0.25 ns, respectively, at a load capacitance of 5 fF. The application of the proposed scheme for realizing multiplexers required in register files is illustrated and compared with the conventional domino logic in the superthreshold, near‐threshold, and subthreshold regions.

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Section: Simulation Results Discussion and Comparisonsmentioning

confidence: 90%

Proposed time‐mode wide fan‐in NAND and NOR gates

Sharroush

Badry

2023

Circuit Theory & Apps

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“…In [49 and 50], the delay variability was reduced by adopting a dual keeper with clock control; this was achieved by reducing the loop gain of the feedback circuitry. In [51], the contention current was reduced using a clock-delayed dual-keeper technique. In addition, by virtue of the stack effect utilized in the keeper circuitry, the size of the keeper could be increased to enhance the robustness of the circuit without sacrificing the speed.…”

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confidence: 99%

A Charge-Accumulation Based High-Performance CMOS Circuit

Sharroush

2022

Port-Said Engineering Research Journal

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There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from degraded performance. In this paper, a circuit that depends on charge accumulation is proposed as an alternative to conventional CMOS design. The proposed scheme is investigated quantitatively and verified by simulation using predictive technology model (PTM) of the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V. Although the proposed scheme suffers from more sensitivity to process variations compared to static CMOS, the comparative analysis and simulation results confirm the superiority of the proposed scheme from the points of view of speed, area, power consumption, and unity-noise gain. It is verified that the proposed scheme has a smaller area, power consumption, and delay compared to the conventional CMOS design when the number of inputs, n, exceeds four, two, and three, respectively. The impacts of process variations, component mismatches, and technology scaling are also investigated. The speed advantage gained from the proposed scheme is expected to be more obvious when operating in the subthreshold region. A figure of merit including the unity-noise gain, area, power consumption, and time delay is defined and the proposed scheme showed superior performance compared to the conventional CMOS logic when n exceeds four. Finally, the proposed scheme was compared with various previous schemes.

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