Speed-independent fused multiply add and subtract unit

Stepchenkov, Yury; Zakharov, Victor; Rogdestvenski, Yuri; Diachenko, Yuri; Morozov, N.V.; Stepchenkov, D.Yu.

doi:10.1109/ewdts.2016.7807735

Cited by 3 publications

(2 citation statements)

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“…This suggests the idea of using two parallel channels, which phases are alternated. Such implementation was presented in [9]- [10]. It had allowed for achieving average 3.15 Gflops performance with synchronous environment and 3.90 Gflops in the absence of unproductive waiting response from a synchronous environment of successful reading result from FMA.…”

Section: A Block Diagram Of Difmasmentioning

confidence: 99%

“…Earlier authors had already attempted to develop speedindependent FMA unit with gigaflops performance SIFMA [7]- [8] and SIFPC [9]- [10]. However, to achieve the maximum performance, SIFMA had utilized a principle of speculative indication that does not provide its absolute self-check ability, while SIFPC was built as two-channel unit with two-stage pipeline having common inputs and outputs, and adaptive indication not considering real size of an isochronous area [11].…”

Section: Introductionmentioning

confidence: 99%

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Delay-Insensitive Floating Point Multiply-Add-Subtract Unit

Соколов

Rogdestvenski

Diachenko

et al. 2019

MES

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The subject of this paper is a floating point unit implementing fused multiply-add-subtract operation. It belongs to the delay-insensitive self-timed (ST) circuits which do not depend on delays both in cells and on wires. It is fully compliant with IEEE 754 Standard and processes both a sum and difference between product of first two operands and third operand. Each 64-bit input operand contains either one double precision number, or two single precision numbers. Thus presented unit calculates either one operation with double precision numbers, or two simultaneous operations with single precision numbers. Multiplier utilizes modified Booth algorithm. In order to increase its performance, it is divided into two pipeline stages with accelerated forced switching to spacer phase. Booth encoder circuit is integrated into an input FIFO. FIFO is implemented as a register file with an output multiplexer and read/write address counters. Using ternary redundant ST code for multiplying, adding and subtracting provides reduction of unit's complexity. Indication subcircuit considers the constrains imposed by an isochronous area for chosen fabrication technology. For decreasing energy consumption, the fused multiply-addsubtract unit implements one-channel pipeline. The unit is designed for 65-nm CMOS bulk technology using an industrial standard cell library supplemented by self-timed cells. It provides 3 Gflops performance and 2.9-ns latency.

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Section: A Block Diagram Of Difmasmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%