2002
DOI: 10.1109/tcsii.2002.801191
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Speed-power-accuracy tradeoff in high-speed CMOS ADCs

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Cited by 122 publications
(74 citation statements)
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“…The supply voltages of RF and analog circuits embedded with digital circuits will decrease to 0.5 V in the near future [2]. Although some calibration techniques have conventionally been used to overcome increasing device mismatch, the architectures of analog signal detection based on conventional A/D converters (ADCs) are approaching their limit in maintaining resolution under such a low voltage supply [3].…”
Section: Introductionmentioning
confidence: 99%
“…The supply voltages of RF and analog circuits embedded with digital circuits will decrease to 0.5 V in the near future [2]. Although some calibration techniques have conventionally been used to overcome increasing device mismatch, the architectures of analog signal detection based on conventional A/D converters (ADCs) are approaching their limit in maintaining resolution under such a low voltage supply [3].…”
Section: Introductionmentioning
confidence: 99%
“…(1, 2), respectively, while the required input signal range is derived as Eqs. (3,4) to operate all the transistors in the saturation region.…”
Section: High-speed Comparator With a Wide Input Rangementioning
confidence: 99%
“…Especially, a reduced input signal range and high comparator offsets at a low supply voltage affect the overall performance of high-speed ADCs [3][4][5]. In case of flash-type ADCs commonly used for high speed conversion with a sampling frequency exceeding several hundreds of MHz, comparators determines most of the overall ADC power dissipation since the number of comparators is exponentially increased with a resolution.…”
Section: Introductionmentioning
confidence: 99%
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