Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic

Christilda, V. Dyana; Milton, A.

doi:10.1007/s10470-021-01853-8

Cited by 24 publications

(5 citation statements)

References 21 publications

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“…Therefore, the wave pipelining technique can be an alternate solution for reducing the area, delay, and clock skew. To achieve this parameter, in wave pipelining and modified wave pipeline approaches, the intermediate latches are removed between input and output registers (12) . The Vedic multiplier with a 16×16 wave-pipeline architecture is shown in Figure 4, where the 16×16 Vedic multiplier is developed by four 8×8 Vedic multipliers.…”

Section: Wave Pipeline Vedic Multipliermentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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Objectives: This work objective is to construct an FPGA-based 16x16 Vedic multiplier and assess the performance of the multiplier using three distinct architectures: pipeline, wave pipeline, and modified wave pipeline in terms of delay and clock skew. Methods: The 16 × 16 Vedic multiplier was constructed and designed through four numbers of an 8x8 Vedic multiplier. For the 16x16 Vedic multiplier, the 3-stage pipeline and wave pipeline techniques are applied, and the delay performances of the Vedic multiplier are compared. Delay optimization: In the wave pipeline Vedic multiplier architecture, the delay is decreased by inserting the known delay on the longest path delay between the multiplier and adder. Clock skew optimization: The clock skew issue of the wave pipeline Vedic multiplier architecture is minimized by adjusting the setup time violation of the clock signal that is connected to the input and output registers. Findings: The delay performance of the Vedic multiplier was evaluated by the synthesis tools Xilinx 12.1, Xilinx ISE 14.2, and Altera, and based on the synthesis report, the Xilinx synthesis tool offers 73.71% delay performance for the pipeline approach and 53.39% for the wave pipeline approach compared to the Altera tool. Further delay is reduced by the proposed modified wave pipeline approach, which saves 2.122 ns of delay compared to the wave pipeline architecture. The clock skew performance was analyzed using the Time Quest timing analyzer tool, and it was minimized to 0.035 from 0.048 compared to the wave pipeline approach. Novelty: In this work, the modified wave pipeline approach has been applied to the existing Vedic multiplier architecture, and it offers less delay as well as less clock skew compared to the existing method. Hence, the performance of the Vedic multiplier with a modified wave pipelined approach was evaluated through a 3-tap FIR filter by applying a vibroarthrography signal. Keywords: Pipeline, Wave Pipeline, Vedic Multiplier, Clock skew, Set up violation, Altera quartex- II Time quest timing analyzer tool

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Section: Wave Pipeline Vedic Multipliermentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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“…Christilda and Milton 33 have presented speed, power, and area efficient 2 dimensional FIR digital filter utilizing Vedic multiplier, predictor, reusable logic. Initially, a predictor blocks used to predict the outputs in Vedic multiplier in terms of prior outputs.…”

Section: Literature Surveymentioning

confidence: 99%

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Mahendran¹,

Kavitha

Radhika³

et al. 2023

Concurrency and Computation

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A design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation based scalable rounding approximate multiplier (APM-CDF-ESDCSA-TOSAM) is proposed in this article for image processing application. The proposed ESDCSA-TOSAM is used to speed up the filter design with less area and less power consumption. In the existing designs, a carry select adder was used that was a rapid binary adders, even though, it consumes maximal area and power. For that reason, lower power, area efficient with higher speed eminent speed dual carry select adder (ESDCSA) is used in this work. The proposed ESDCSA is a fastest binary adder, which consumes less power and area. To design the ESDCSA, three blocks are used: half sum with carry generator (HSCG), final carry generator (FCG), final sum generator (FSG), these are reducing the power and area. TOSAM is used to reduce more partial products by truncating each input operands depending on its leading one-bit position.The proposed filter is designed on Xilinx ISE 14.5 design tools. The experimental performance of the proposed filter attains lower delay 59.61%,

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“…Christilda and Milton 32 have presented a Speed, power and area efficient 2D FIR digital filter using Vedic multiplier with predictor and reusable logic. To optimize speed, area and power, two models were utilized.…”

Section: Literature Surveymentioning

confidence: 99%

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

Senthilkumar¹,

Pandi

Sripriya

et al. 2023

Concurrency and Computation

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Summary Recustomize finite impulse response (RFIR) filter is designed to achieve lesser power consume, cost, area, and higher speed of system operation. This is used to remove the noises from the image and signal. Previously, several filters were designed for removing noises, but that filters consume more area, power, cost, and delay and did not provide accurate results and the error rate was increased. To overcome these issues, this work is proposed. In this work, the Recustomize finite impulse response (RFIR) filter is designed using truncation‐based scalable rounding approximate multiplier (TOSAM) and error reduced carry prediction approximate adder (ERCPAA) for image processing application. Here, TOSAM‐ERCPAA is used to speed up the filter design with less area and less power consumption. The proposed ERCPAA adder is divided into three blocks, such as carry prediction logic, approximate full adder cells array, constant truncation along error lessening logic, which can reduce the power and area. The proposed RFIR‐ TOSAM‐ERCPAA filter is designed and executed in Verilog programming language and the simulation is done in Xilinx ISE 14.5 design tools.

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Speed, power and area efficient 2D FIR digital filter using vedic multiplier with predictor and reusable logic

Cited by 24 publications

References 21 publications

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Design of all pass make over based capricious digital filter using eminent speed dual carry select adder and truncation and rounding approximate multiplier for image processing application

Design of recustomize finite impulse response filter using truncation based scalable rounding approximate multiplier and error reduced carry prediction approximate adder for image processing application

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