Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals

Fiege, Nicolai; Sittel, Patrick; Zipf, Peter

doi:10.1109/fpl57034.2022.00056

2022 32nd International Conference on Field-Programmable Logic and Applications (FPL) 2022

DOI: 10.1109/fpl57034.2022.00056

|View full text |Cite

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals

Nicolai Fiege

Patrick Sittel

Peter Zipf

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2023

Publication Types

Select...

Article1

Relationship

Self Cite0

Independent1

Authors

Journals

Cited by 1 publication

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Fiege

Zipf

2023

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

Modulo scheduling is the premier technique for throughput maximization of loops in high-level synthesis by interleaving consecutive loop iterations. The number of clock cycles between data insertions is called initiation interval (II). For throughput maximization, this value should be as low as possible; therefore its minimization is the main optimization goal. Despite its long historical existence, modulo scheduling always remained a relevant research topic over the last years with many exact and heuristic algorithms available in literature. Nevertheless, we are able to leverage the scalability of modern Boolean Satisfiability (SAT) solvers to outperform state-of-the-art ILP-based algorithms for latency-optimal modulo scheduling for both integer and rational IIs. Our algorithm is able to compute valid modulo schedules for the whole CHStone and MachSuite benchmark suites, with 99% of the solutions being proven to be throughput-optimal for a timeout of only 10 min per candidate II. For various time limits, not a single tested scheduler from the state-of-the-art is able to compute more verified optimal solutions or even a single schedule with a higher throughput than our proposed approach. Using an HLS toolflow we show that our algorithm can be effectively used to generate Pareto-optimal FPGA implementations regarding throughput and resource usage.

show abstract

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Fiege

Zipf

2023

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals

Cited by 1 publication

References 15 publications

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining

Contact Info

Product

Resources

About