Speeding-up the design of HW/SW implementations of neuro-fuzzy systems using the CodeSimulink environment

Reyneri, Leonardo; Renga, Flavio

doi:10.1016/j.asoc.2004.03.003

Cited by 12 publications

(5 citation statements)

References 14 publications

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“…At first the system has been simulated thoroughly by means of the CodeSimulink [12,13]. Simulations have been used to assess the actual performance of the method, in the presence of a number of parasitic parameters.…”

Section: Simulations and Sensitivitymentioning

confidence: 99%

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's

Venuto

Reyneri

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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This work describes a novel test strategy that uses digital stimuli for cheap, fast, though accurate, testing of high resolution Σ∆ ADC's. Simulation results showed a detection sensitivity on specifications parameters of up to -100dB. The proposed method can also help to reduce the cost of ADC production test, to extend test coverage and to enable built-in self-test and test-based self-calibration.

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Section: Simulations and Sensitivitymentioning

confidence: 99%

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's

Venuto

Reyneri

2007

8th International Symposium on Quality Electronic Design (ISQED'07)

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“…The section of instruction, which improves Neurofuzzy calculation most efficiently, is performed using hardware/software co-evaluation techniques. This approach combines software evaluation methods with hardware synthesis of the application-specific processor to collect data for the evaluation process [11][12][13][14][15]. Software evaluation establisher the cycle count and logic synthesis estimates cycle time and chip area.…”

Section: Introductionmentioning

confidence: 99%

MIPS-NF instructions for fourth generation processor

Ansari

Gupta²

2009

2009 2nd International Conference on Computer, Control and Communication

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In this paper we describe general purpose RISC processor with specialized Neurofuzzy control operations to achieve high Neurofuzzy processing performance. As a case study we show the definition & evaluation of instruction set extension for Neurofuzzy processing. We have extended the MIPS instruction set architecture with only a few new instructions to significantly speed up Neurofuzzy computation. These instructions are based on the use of subword parallelism to fully exploit the processor's resources by processing multiple data steam in parallel. We have found that a simple instruction optimized to perform Neurofuzzy rule evaluation offers the most benefit to improve Neurofuzzy processing performance.

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“…: n=512, 1024, 2048 in the suitable way. The value n is related to the low-pass filter bandwidth, and then to its time constant , as follows: S f N 16 (9) .Different pole frequencies: 1.5krad/s, 750rad/s, 375rad/s, were considered by changing the feedback capacitor in the filter. Moreover a PWM phase of 0, 0.25, 0.5, 0.75, has been considered.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Investigations have been performed by using CodeSimulink [9], a codesign tool suitable to: 1. cosimulate the analog, digital and mixed-signal parts of the system under study; 2. design, simulate and tune the digital HW for the proposed method and to generate VHDL code for the FPGA. Starting from system description, it is possible to compile the whole system or part of it, in order to program the FPGA with the best performance and lower cells occupancy.…”

Section: Simulation Tool and Modelmentioning

confidence: 99%

“…In this paper, the authors will describe the test strategy showing the measurements results obtained by testing with such technique a commercial CODEC. The combination of the simulations performed by using a recently developed software tool CodeSimulink [9] and the measurements show the limits of the method and also allow the introduction of further improvements.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs

Venuto

Reyneri

7th International Symposium on Quality Electronic Design (ISQED'06)

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This work describes an intensive investigation on the test strategy known as polynomial fitting that uses FPGA generated stimuli for cheap and fast testing of high resolution ADC's. Simulation and experimental results showed a sensitivity on the specifications parameters detection of 90dB. The proposed method can also help to control the cost of ADC production test, extends the test coverage and enable built-in self-test and test-based selfcalibration.

show abstract

Speeding-up the design of HW/SW implementations of neuro-fuzzy systems using the CodeSimulink environment

Cited by 12 publications

References 14 publications

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's

Fully Digital Optimized Testing and Calibration Technique for \Sigma \Delta ADC's

MIPS-NF instructions for fourth generation processor

Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs

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