Speedy bus mastering PCI express

Abstract

PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in FPGAs is limited and/or expensive. The Speedy PCIe core addresses this problem by bridging the gap from the bare bones interface to a user friendly, high performance design. This paper describes some of the fundamental design challenges and how they were addressed as well as giving detailed results. The hardware and software source code are available for free download from [12].

An efficient and flexible host-FPGA PCIe communication library

“…It runs under PCIe Gen1 X4 mode with 3.04Gbps DMA read rate and 5.6Gbps DMA write rate. It has limitations similar to those of Speedy Bus Master [3].…”

“…Speedy Bus Mastering PCI Express [3] is a PCIe communication library implemented on Xilinx Virtex-5 and Virtex-6 FPGAs. It provides a solution that maps the PCIe bus to a local bus.…”

SAccO: An implementation platform for scalable FPGA accelerators

“…The support packages provided by the board vendors only provide base functionality on a low level [15][16][17]. Only the Speedy PCIe Core [18] and the RIFFA2.0 [19] projects, which were published after we started our project, follow a similar approach to ours also using PCIe. The implementations of the earlier versions of these projects [20,21] were too slow for our project.…”

Implementation of High-Speed Serial Interconnects for Multi-Processor Parallel System

“…This specification describes operations for x1, x2, x4, x8, x12, x16, and x32 lane widths. PCIe is often regarded as one of the main interfaces to connect board to PC [7,8]. Because key PCI attributes, such as its usage model, load-store architecture, and software interfaces, are maintained, whereas its parallel bus implementation is replaced by a highly scalable, fully serial interface.…”