SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET

Abstract

The tunnel field-effect transistor (TFET) is one of the promising transistors which is expected to replace some complementary metal-oxide semiconductor (CMOS) circuits. Here, we apply a SPICE simulation of a Si TFET using high-K gate insulator to a simple circuit of 32-kHz crystal oscillator and compare the power consumption of Si TFET with conventional CMOSs calculated from the predictive transistor model (PTM). We considered L = 65-nm and L = 90-nm devices based on a table model whose values are derived from technology computer aided design (TCAD) calculations. We show that the power consumptions of TFETs are about 22.3%∼38.6% lower than those of CMOSs for L = 65-nm devices, and we show the 13.6%∼36.1% lower power consumption of TFETs for L = 90nm devices.

Optimization of spacer and source/channel junction to improve TFET characteristics

“…When a supply voltage (Vdd) is lowered for the low power applications, it is essential to lower a subthreshold swing (S) to maintain a high ON-state current (Ion) and a low OFF-state current (Ioff). However, as the metaloxide-semiconductor field-effect transistors (MOSFETs) cannot reduce S below 60 mV/dec at room temperature due to its fundamental limitations [1,2], several new devices such as positive feedback FETs [3,4], negative capacitance FETs (NCFETs) [5,6,7], nano-electro mechanical FETs (NEMFETs) [8,9] and tunnel FETs (TFETs) [10,11,12,13,14,15] are being explored as alternatives. Among them, TFETs are devices using band-to-band tunneling between source and channel as a current driving mechanism, and have received much attention because of those high compatibility with conventional complementary MOS (CMOS) processes [16,17].…”