Spin-Orbit-Torque Magnetic Tunnel Junction Transistor Based Area Efficient Low Power Non-Volatile Master-Slave Flip-Flop

Abstract

A Spin Orbit Torque (SOT) Magnetic-Tunnel-Junction (MTJ) transistor based area efficient F) is discussed in this paper. The modified NV-MSFF has consumed less area and less power consumption when compared to the existing NV-MSFF. Hence, the proposed NV-MSFF is more suitable for low power applications. The proposed NV-MSFF is designed and implemented as hybrid CMOS-Spintronics circuit using 45 nm CMOS process technology and Verilog-A model based MTJ-Transistor for Spintronics. The proposed NV-MSFF has been designed and simulated using Cadence Virtuoso-Analog-Design-Environment (ADE) with Spectre as the simulator and the simulation temperature as 27°C. The proposed NV-MSFF has 44% reduction in the area occupied. The overall energy requirement of the prevailing NV-MSFF is 1.961 µW whereas it is 194.2 nW only for modified NV-MSFF. The delay of the existing NV-MSFF is 1.175 ns whereas it is 383.3 ps only for the modified NV-MSFF. The proposed NV-MSFF outperforms in terms of area, power and the propagation time.