Spin Wave Based Full Adder

Mahmoud, Abdulqader; Vanderveken, Frederic; Ciubotaru, Florin; Adelmann, Christoph; Cotofana, Sorin; Hamdioui, Said

doi:10.36227/techrxiv.16616134

Cited by 2 publications

(3 citation statements)

References 21 publications

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“…The proposed methodology could be exploited to compare all-magnon circuits with state-of-the-art spintronic technologies, i.e. the FA design proposed in [45].…”

Section: Discussionmentioning

confidence: 99%

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

Garlando

Wang

Dobrovolskiy

et al. 2023

IEEE Trans. Emerg. Topics Comput.

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In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic blocks to enable the design and simulation of magnonic gates and magnonic circuits of arbitrary complexity and demonstrate its functionality on the example of a 32-bit integrated RCA. It is shown that the RCA requires the utilization of additional regenerators based on magnonic directional couplers with embedded amplifiers to normalize the magnon signals in-between the half-adders. The benchmarking of large-scale magnonic integrated circuits is performed. The energy consumption of 30 nm-based magnonic 32-bit adder can be as low as 961 aJ per operation with taking into account all required amplifiers.

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“…The proposed methodology could be exploited to compare all-magnon circuits with state-of-the-art spintronic technologies, i.e. the FA design proposed in [45].…”

Section: Discussionmentioning

confidence: 99%

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

Garlando

Wang

Dobrovolskiy

et al. 2023

IEEE Trans. Emerg. Topics Comput.

View full text Add to dashboard Cite

show abstract

“…Furthermore, AFA consumes approximately 4 and 3 orders of magnitude less energy while providing 38% and 8% lower delay in comparison with the accurate and approximate Spin-CMOS based FAs, respectively, while having the same error rate as the approximate FA in [33]. Last but not least, AFA outperforms the SW based accurate FA [36] by diminishing the energy consumption and delay with 38% and 35%, respectively. Note that, as a chip real-estate estimation, the proposed approximate FA requires the lowest number of devices.…”

Section: Performance Evaluationmentioning

confidence: 90%

“…To gain more insight into the practical implications of our proposal, we compare the AFA with the state-of-the-art accurate SW [36], 7nm CMOS [37], SHE [38], DWM [39], accurate and approximate 45nm CMOS [40], MTJ [41], and Spin-CMOS [33] counterparts in terms of energy, delay, and area (the number of utilized devices). We base our evaluation on the following assumptions: (i) Magnetoelectric (ME) cells are utilized for SW excitation and detection.…”

Section: Performance Evaluationmentioning

confidence: 99%

Spin Wave Based Approximate Computing

Mahmoud

Vanderveken

Ciubotaru

et al. 2022

IEEE Trans. Emerg. Topics Comput.

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By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits, as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications, e.g., multimedia and social media, are error-tolerant. In this paper, we propose an ultra-low energy Approximate Full Adder (AFA) and an Approximate 2-bit inputs Multiplier (AMUL). AFA consists of one Majority gate whereas AMUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate AFA's figures of merit against state-of-the-art accurate SW, 7nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 38% and 6% less energy than state-of-the-art accurate SW and 7nm CMOS FA implementations, respectively. Moreover, it saves 56% and 20% energy when compared with accurate and approximate 45nm CMOS counterparts, respectively. Furthermore, it provides 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nm CMOS and Spin-CMOS FAs whereas it exhibits 50% less error rate than the approximate DWM FA. Last but not least, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art SW and 16nm CMOS accurate and approximate designs. The evaluation results indicate that AMUL energy consumption is at least 2.8x and 2.6x smaller than the one of state-of-the-art SW and 16nm CMOS accurate and approximate designs, respectively. AMUL has an error rate of 25%, whereas the approximate CMOS multiplier has an error rate of 38%, and requires at least 64% less chip real-estate than the CMOS counterpart.

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Spin Wave Based Full Adder

Cited by 2 publications

References 21 publications

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

Numerical Model for 32-Bit Magnonic Ripple Carry Adder

Spin Wave Based Approximate Computing

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