/spl mu/Complexity: estimating processor design effort

Bazeghi, Cyrus; Mesa-Martinez, Francisco J.; Renau, Jose

doi:10.1109/micro.2005.37

Cited by 21 publications

(34 citation statements)

References 5 publications

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“…We employ five open-source hardware designs in our experiments, where four designs (ethmac, openMSP430, or1200, vga lcd) are from OpenCores, 3 and one (non router) is an open-source project of Stanford University. 4 They cover different application fields, such as processors (or1200), communication controller (ethmac), video controller (vga lcd) and so on.…”

Section: A Datasetsmentioning

confidence: 99%

“…Protheroe et al [28] provided some characteristics on RTL of a design to evaluate the design quality. Bazeghi et al [3] studied characteristics of hardware description languages (HDL) code and results provided by design compiler to estimate design effort of microprocessors. There are also investigations on the bug analysis of hardware designs.…”

Section: A Complexity Characteristics and Bug Analysismentioning

confidence: 99%

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Pre-Silicon Bug Forecast

Guo

Chen

Wang³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The ever-intensifying time-to-market pressure imposes great challenges on the pre-silicon design phase of hardware. Before the tape-out, a pre-silicon design has to be thoroughly inspected by time-consuming functional verification and code review to exclude bugs. For functional verification and code review, a critical issue determining their efficiency is the allocation of resources (e.g., computational resources and manpower) to different modules of a design, which is conventionally guided by designers' experiences. Such practices, though simple and straightforward, may take high risks of wasting resources on bugfree modules or missing bugs in buggy modules, and thus could affect the success and timeline of the tape-out. In this paper, we propose a novel framework called pre-silicon bug forecast to predict the bug information of hardware designs. In this framework, bug models are built via machine learning techniques to characterize the relationship between design characteristics and the bug information, which can be leveraged to predict how bugs distribute in different modules of the current design. Such predicted bug information is adequate to regulate the resources among different modules to achieve efficient functional verification and code review. To evaluate the effectiveness of the proposed pre-silicon bug forecast framework, we conducted detailed experiments on several open-source hardware projects. Moreover, we also investigate the impacts of different learning techniques and different sets of characteristic on the performance of bug models. Experimental results show that with appropriate learning techniques and characteristics, about 90% modules could be correctly predicted as buggy or clean and the number of bugs of each module could also be accurately predicted.

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Section: A Datasetsmentioning

confidence: 99%

Section: A Complexity Characteristics and Bug Analysismentioning

confidence: 99%

Pre-Silicon Bug Forecast

Guo

Chen

Wang³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…While the work described in this paper focuses on PCB design metrics, [1] uses a similar regression model, but both papers analyze different sets of statistics and targets.…”

Section: Related Workmentioning

confidence: 99%

“…The aggregate of the statistics is inversely proportional to the productivity of a specific design team which is represented by a constant (ρ). The model is presented in Equation 1. In order to find suitable values for each of the data weights (w i ) we perform mixed non-linear regressions on this equation.…”

Section: Approachmentioning

confidence: 99%

“…We present in this paper a first step toward creating a design effort metric that is highly correlated with design effort for PCB layout. We follow a similar approach taken in [1] as the principles that are applicable to microprocessors are also This work was supported in part by the National Science Foundation under grants 0546819 and 720913; Special Research Grant from the University of California, Santa Cruz; and gifts from SUN. applicable to PCBs. In this paper, design effort corresponds to the number of engineering-hours required for implementation (layout) of a PCB design.…”

Section: Introductionmentioning

confidence: 99%

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Estimating design time for system circuits

Bazeghi

Mesa-Martinez

Greskamp

et al. 2007

2007 IFIP International Conference on Very Large Scale Integration

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System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it will take to design and verify these designs, which are getting denser and increasingly more complex. To compound this problem, circuit design cost estimation still does not have a quantitative approach. Although designing a system is very resource consuming, there is little work invested in measuring, understanding, and estimating the effort required.To address part of the current shortcomings, this paper introduces µPCBComplexity, a methodology to measure and estimate PCB (printed circuit board) design effort. PCBs are the central component of many systems and require large amounts of resources to properly design and verify. µPCBComplexity consists of two main parts; a procedure to account for the contributions of the different elements in the design, and a non-linear statistical regression of experimental measures in order to determine a good design effort metric. We use µPCBComplexity to evaluate a series of design effort estimators for twelve PCB designs. By using the proposed µPCBComplexity metric, designers can estimate PCB design effort.

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System and Procesor Design Effort Estimation

Bazeghi

Mesa-Martinez

Renau

2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Design complexity is rapidly becoming a limiting factor in the design of modern high-performance digital systems. The increasing levels of design effort required to improve and implement critical processor and system structures have led to staggering design costs. As we design ever larger and more complex systems, it is becoming increasingly difficult to estimate how much time it takes to design and verify them. Novel quantitative and optimization approaches are needed to understand and deal with the limiting effects induced by design complexity, which remain for the most part hidden from the architect. To address part of these shortcomings, this work introduces µComplexity and µPCBComplexity, a set of methodologies to measure and estimate design effort for modern processor and PCB (printed circuit board) designs.

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/spl mu/Complexity: estimating processor design effort

Cited by 21 publications

References 5 publications

Pre-Silicon Bug Forecast

Pre-Silicon Bug Forecast

Estimating design time for system circuits

System and Procesor Design Effort Estimation

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