Splatty- A Unified Image Demosaicing and Rectification Method

Verma, Pranav; Meyer, Dominique; Xu, Hanyang; Kuester, Falko

doi:10.1109/wacv48630.2021.00083

Cited by 1 publication

(1 citation statement)

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“…This design flow enables engineers to reduce their development times and to better link their final HDL algorithm implementation to the high level algorithm simulation model. Future work entails potentially combining the demosaicing and the rectification operations into a single process as is demonstrated in [22] and using HDL Coder to auto-generate the associated IP core. With larger FPGA fabrics it may also be beneficial to convert the entire algorithm into floating point logic such that the fixed point datapath does not need to be tweaked for various image sensors.…”

Section: Discussionmentioning

confidence: 99%

Model Based Design of a Real Time FPGA-Based Lens Undistortion and Image Rectification Algorithm for Stereo Imaging

Kaputa

Derhak

2023

IEEE Access

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Low cost imaging sensors and powerful embedded computers have taken the field of computer vision to new heights. One of the challenges that remains is to shorten the development time that it takes to target one's algorithm to hardware. This work details the steps necessary to use Model Based Design to first simulate and then to target a stereo rectification and undistortion algorithm to an embedded FPGA system on chip hardware target. This work demonstrates what the future of FPGA-based algorithm development might look like by making use of closed loop design techniques with the aid of novel Model Based Design tool flows. Hardware-abstracted constructs such as 'virtual cameras' and the capability of pulling images off the target system and feeding them back into the simulation model help to minimize discrepancies between simulation and hardware domains, ultimately reducing the total development time. The developed system is a deterministic real time and low latency implementation as it does not rely on external off chip memory as all necessary buffering is done in the internal FPGA block RAM structures. The design is capable of processing 752x480 images at pixel line rates and is easily expandable to high resolution images. The algorithm being developed is not being touted as novel, rather that it is sufficiently complex in order to demonstrate the power of the Model Based Design tool flows.

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Section: Discussionmentioning

confidence: 99%