Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs

Abstract

A fully deterministic digital background calibration for pipeline ADCs is presented. The proposed approach is based on split ADC concept to give the shortest background calibration time with high accuracy. A slope mismatch averaging technique is employed in a multistage calibration scheme to deterministically detect the circuit errors without any iterative operations or feedback loops, which render it fast and accurate. Analysis and behavioral simulations for the developed multistage calibration demonstrate the efficiency of this technique and its merit over the LMS-based techniques. Practical considerations have been considered and the proposed calibration has been applied on a 200 MS/s 40 nm CMOS split pipeline ADC to correct for the capacitor mismatch and the amplifier finite gain. The post-layout simulation results show a very fast calibration cycle, where the ADC achieves more than 11 ENOB in less than 1600 clock cycles.

Analog to Digital Converters (ADC): A Literature Review

“…The calibration was performed on a 200MS/s 40 nm CMOS for the modification in capacitor mismatch and amplifier gain. In this article, the behavioural simulation proved the area and power of the implemented 40nm 12-bit pipelined ADC 0.42mm 2 and 54 mW [11].…”

“…Split ADC background calibration concept [11] Another work by A. Fahmy et al on stochastic ADC was explained with its programmability and reconfigurability by dividing the whole design into 8 channels with a 10-bit control word. Using Verilog and digital design tools for synthesis fabricated on 130nm CMOS process, results were obtained in terms of SFDR and SNDR at 0.7V supply [12].…”