Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

Abstract

This paper presents the linearity analysis of a successive approximation registers (SAR) analog-to-digital converters (ADC) with split DAC structure based on two switching methods: conventional charge-redistribution and V cm -based switching. The static linearity performance, namely the integral nonlinearity and differential nonlinearity, as well as the parasitic effects of the split DAC, are analyzed hereunder. In addition, a code-randomized calibration technique is proposed to correct the conversion nonlinearity in the conventional SAR ADC, which is verified by behavioral simulations, as well as measured results. Performances of both switching methods are demonstrated in 90 nm CMOS. Measurement results of power, speed, and linearity clearly show the benefits of using V cm -based switching.

A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter

“…The capacitor arrays are used as the sampling capacitors as well as the part of the DACs. Two-stage weighted capacitor arrays with attenuated capacitor [6], [9] are widely used to minimize its total capacitance and to improve the power efficiency. However, it causes the linearity problem A 100-nW 9. between two sub-DACs, and requires additional calibration operation [9].…”

“…From the MSB-2 to LSB bit cycling, the proposed CDAC operates as pseudo single-ended fashion and power supply noise might affect the ADC performance. For a 10-b accuracy, the V ref /4 variation should be suppressed within ±0.1% of the V ref /4 [6]. The precise low-noise voltage regulator and the decoupling capacitors help to alleviate this limitation.…”

“…When we assume that the unit capacitance is identical in each switching method for the 10-bit capacitor array, the proposed scheme reduces the energy consumption by 97%, 89%, 84%, 76% and 68% compared with the conventional [8], switchback with reset energy [7], monotonic [4], and Vcm-based [6] approaches, respectively. Fig.…”

“…Increasing the ADC resolution requires larger capacitor arrays and increasing the capacitor switching energy. Several CDAC switching techniques, such as split capacitor [2], energy saving [3], monotonic [4], charge redistribution [5], Vcm-based [6], and switchback [7] have been researched to minimize the CDAC switching energy.…”

A split transconductor high-speed SAR ADC

“…Another limit of the split SAR scheme comes from the parasitic capacitances. When using very small unity elements, the capacitance of metal routing becomes significant and influences the attenuation factor, [5] [6] [7]. This requires digital calibration, [8], that, for a 28 nm technology and C U = 4.4 fF, becomes necessary even for 8-bit accuracy.…”