Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΔΣ modulator with level shifter

Kokubo, Masaru; Kimura, Takashi; Oshima, Takashi; Noto, Takayuki; Suzuki, Mariko; Suzuki, Shuji; Hirose, Takashi; Tomoaki, Takahashi; Jun, Kasai

doi:10.1109/isscc.2005.1493918

Cited by 60 publications

(32 citation statements)

References 2 publications

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“…The 8-bit counter output represents the profile slope and the 'Sign' output indicates the sign of the profile slope (positive or negative). Since the 8-bit up/down counter (SM counter) is used, the slope variation resolution is the 1/2 8 . When the SSCG operates, the SM counter repetitively sweeps the output from 'K' to 0.…”

Section: Architecture and Operationmentioning

confidence: 99%

“…(1) [11]. 8 Output value of SM counter AVS = 2 (1) The half period of the triangular slope curve is a quarter of the modulation period as shown in Fig. 3.…”

Section: Architecture and Operationmentioning

confidence: 99%

“…In prior works the Hersey-Kiss profile or Hersey-Kiss-like profile was generated by look-up-table (LUT) [2], SRAM [3], piecewise linear modulation [4], and a Newton-Raphson method design [5]. Other various approaches are also reported [6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

Oh¹,

Park²,

Moon³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a 0.13 µm CMOS technology.

show abstract

Section: Architecture and Operationmentioning

confidence: 99%

“…(1) [11]. 8 Output value of SM counter AVS = 2 (1) The half period of the triangular slope curve is a quarter of the modulation period as shown in Fig. 3.…”

Section: Architecture and Operationmentioning

confidence: 99%

See 1 more Smart Citation

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

Oh¹,

Park²,

Moon³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…Among several methods of the EMI reduction, using a spread-spectrum clock generator (SSCG) based on a DS PLL is considered a viable solution with full digital control and fine resolution [1][2][3][4]. The 1-bit timeto-digital converter (TDC) or the bang-bang phase detector (BBPD) enables a low-complexity digital PLL (DPLL) design and offers easy design migration from the traditional PLL by explicitly having the frequency divider.…”

Section: Introductionmentioning

confidence: 99%

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Xu¹,

Shen²,

Lv³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a spread-spectrum clock generation method by utilizing a DS digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order DS modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The DS DPLL employs a twopoint modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

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“…The serialto-parallel converter (S/P) converts from the DATA to the received parallel data (RD) by using the CLK. In this SATA-PHY, the SSCG is applied a fractional SSCG because of a large EMI reduction [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The fractional SSCG should be narrow loop bandwidth because the quantized noise originated from a ΣΔ modulator is removed.…”

Section: Introductionmentioning

confidence: 99%

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

Kimura

Suzuki

Noto

2015

Journal of Electrical and Computer Engineering

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A low-jitter fractional spread-spectrum clock generator (SSCG) utilizing a fast-settling dual-charge-pump (CP) technique is developed for serial-advanced technology attachment (SATA) applications. The dual-CP architecture reduces a design area to 60% by shrinking an effective capacitance of a loop filter. Moreover, the settling-time is reduced by 4 s to charge a current to the capacitor by only main-CP in initial period in settling-time. The SSCG is fabricated in a 0.13 m CMOS and achieves settling time of 3.91 s faster than 8.11 s of a conventional SSCG. The random jitter and total jitter at 250 cycles at 1.5 GHz are less than 3.2 and 10.7 psrms, respectively. The triangular modulation signal frequency is 31.5 kHz and the modulation deviation is from −5000 ppm to 0 ppm at 1.5 GHz. The EMI reduction is 10.0 dB. The design area and power consumption are 300 × 700 m and 18 mW, respectively.

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Spread-spectrum clock generator for serial ATA using fractional PLL controlled by ΔΣ modulator with level shifter

Cited by 60 publications

References 2 publications

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

A Spread Spectrum Clock Generator for DisplayPort 1.2 with a Hershey-Kiss Modulation Profile

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications

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