Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation

Sotiriadis, Paul P.

doi:10.1109/tcsi.2016.2525058

Cited by 23 publications

(4 citation statements)

References 17 publications

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“…In order to avoid the delay of the frequency control and make the whole process smoother, the implementation and disadvantage of the conventional carrier generation method are discussed in detail. Then, a brief introduction to the direct digital frequency synthesizer (DDS) theory [45], [46] is done. Based on DDS, a wait-free phase-continuous carrier frequency modulation strategy (WPCFM), easy to implement, is proposed.…”

mentioning

confidence: 99%

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

Chen

Yang

Long

et al. 2019

IEEE Trans. Power Electron.

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In AC motor drives, the fixed-frequencies harmonic components of output voltage and current from the inverter with fixed frequency pulse width modulation (FFPWM) usually lead to electromagnetic interference (EMI). The spread spectrum clock generation (SSCG) is a widely used solution of this problem. Adjusting the switching frequency to reduce EMI is one kind of practicable scheme among SSCG methods. How to design an optimal or suitable modulation profile is a research emphasis of scholars and has been discussed in depth in many literatures. However, apart from modulation profile, the mode and quality of carrier are also important and can be improved. In most frequency modulation methods, due to the limitation of the conventional carrier generation mode, the implementation of the new frequency instruction has to wait to the termination of the last switching period. In order to eliminate the waiting state and design a simpler algorithm, this paper has proposed a wait-free phase-continuous carrier frequency modulation strategy (WPCFM) by combining the direct digital frequency synthesizer (DDS) theory and proper temporal planning of control interruptions. Besides, theoretical analysis of WPCFM including quantization error, frequency jitter, phase delay and voltage distortion have been finished. Moreover, compared with conventional methods, a more convenient, feasible and simpler field-programmable gate array (FPGA) based algorithm implementation method and the control structure of WPCFM are also introduced. Analysis shows that, although WPCFM causes a slight increase of the current ripple, it can solve the partial frequency nonuniform distribution problem of conventional method and it has potential value of applications in the wide band gap (WBG) motor drive systems. The effectiveness of the WPCFM is verified by several sets of EMI reduction experiments where classical periodic carrier frequency modulations are applied. 1

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mentioning

confidence: 99%

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

Chen

Yang

Long

et al. 2019

IEEE Trans. Power Electron.

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“…Since the right-hand side of (20) is independent of t, the output signal s(t) is in fact wide sense stationary (WSS). Let S(ω) denote the PSD of s(t), which is related to R s (τ ) by A comparison of (21) and (20) shows that…”

Section: Mathematical Model Of Dithering Dtc-based Frequency Synmentioning

confidence: 99%

“…For more information, see https://creativecommons.org/licenses/by/4.0/ dithering methods discussed in this work are also applicable in that scenario. In [20], [21] dithering concepts are presented to counter the effects of the deterministic jitter due to low resolution and nonlinearities.…”

mentioning

confidence: 99%

Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers

Preissl

Preyler

Springer

et al. 2021

IEEE Trans. Circuits Syst. I

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Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dithering. This work presents a mathematical model for dithering DTC-based local oscillator (LO) generators. It proposes concepts for the application of subtractive dither and it introduces a novel generalization of quantization-dither to allow for optimal dithering of nonlinear quantizers.

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“…DDS architectures are even appearing in low-pass filtered single bit output form by PWM [WMR + 04] or delta-sigma modulation [SADRH08,Sot16]. These architectures can take some advantage of the continuous digital scaling, not only benefiting from the increased speed of sub-micron processes but also the integration of power and area efficient digital logic in the same technology.…”

Section: Summary Of Thesis and Published Papersmentioning

confidence: 99%

UWB waveform generator for digital CMOS radar

Bjorndal

Hamran

Lande³

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Small, low cost, radar systems have exciting applications in monitoring and imaging for the industrial, healthcare and Internet of Things (IoT) sectors. We here explore, and show the feasibility of, several single bit square wave radar architectures; that benefits from the continuous improvement in digital technologies for system-on-chip digital integration. By analysis, simulation and measurements we explore novel and harmonic-rich continuous wave (CW), stepped-frequency CW (SFCW) and frequency-modulated CW (FMCW) architectures, where harmonics can not only be suppressed but even utilized for improvements in down-range resolution without increasing on airbandwidth. In addition, due to the flexible digital CMOS implementation, the system is proved by measurement, to feasibly implement pseudo-random noise-sequence and pulsed radars, simply by swapping out the digital baseband processing. Single bit quantization is explored in detail, showing the benefits of simple implementation, the feasibility of continuous time design and only slightly degraded signal quality in noisy environments compared to an idealized analog system. Several iterations of a proof-of-concept 90 nm CMOS chip is developed, achieving a time resolution of 65 ps at nominal 1.2 V supply with a novel Digital-to-Time converter architecture. In pulsed mode, the chip features programmable pulses with a minimum width of 130 ps and a time step of 65 ps. In CW mode, we can transmit arbitrary signals up to 3.8 GHz all the way down to DC. With a continuous time single bit receiver, the backscattered signal can be mixed with the on-chip XOR gate and integrated with the on-chip counters, to provide a system-on-chip CW platform.iii

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Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation

Cited by 23 publications

References 17 publications

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

A DDS-Based Wait-Free Phase-Continuous Carrier Frequency Modulation Strategy for EMI Reduction in FPGA-Based Motor Drive

Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers

UWB waveform generator for digital CMOS radar

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