SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri, Nabiollah; Sadeghi, Ayoub; Rafiee, Mahmood; Bigonah, Maryam

doi:10.1002/cta.3251

Cited by 9 publications

(4 citation statements)

References 53 publications

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“…The layout chip area estimation of the proposed SRAM bitcell.-Figure 9 depicts the 3-D and 2-D chip layouts view for 1 × 1 memory array based on proposed UPRHSE bit-cell in the standard cell form using the CAD electric-VLSI Design tool with the mocmoscn technology library, 46 where the minimum feature size i.e. half of the physical gate length (λ)-based rules in a 16 nm feature size for achieving the optimum power consumption is considered.…”

Section: Simulation Results Comparative Analysis and Discussionmentioning

confidence: 99%

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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We propose a novel design of an ultra-low power radiation-hardened single-ended (UPRHSE) SRAM bit-cell using the GAA CNT-GDI method. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors is proposed. The results of extensive Monte-Carlo simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to PVT variations, and higher critical charge. Moreover, the suggested bit-cell has more robustness to soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in other comprehensive figures of merit as compared to state-of-the-art bit-cells in the 16 nm technology. Finally, the proposed bit-cell in a real application is used to store data from two-layer quick-response code-based in terrestrial environments. The results show better performance of the bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs.

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Section: Simulation Results Comparative Analysis and Discussionmentioning

confidence: 99%

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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“…It is worth mentioning to achieve a fair and realistic evaluation, and we redesigned our schemes in 16‐nm technology. Figure 5 depicts the 2‐D and 3‐D chip layouts view for the 1 × 1 memory array using the CAD electric‐VLSI Design tool with the mocmos‐cn technology library 14 . The physical chip layout size of the memory mini‐array is about 25 μm 2 .…”

Section: Simulation Results Comparative Analysis and Supplementary Di...mentioning

confidence: 99%

“…Figure 5 depicts the 2-D and 3-D chip layouts view for the 1 Â 1 memory array using the CAD electric-VLSI Design tool with the mocmos-cn technology library. 14 The physical chip layout size of the memory mini-array is about 25 μm 2 . 6B, it can be seen that due to the use of the asymmetric write-assist scheme, the Write-VTC (WVTC) of the proposed cell is straight and without curvature.…”

Section: Simulation Setup and Layout Chip Area Estimation Of Proposed...mentioning

confidence: 99%

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Darabi

Salehi

Abiri

2022

Circuit Theory & Apps

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This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms.

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“…Since the main aim of the proposed cell design is to lower the power consumption without losing special features like the drivability and full‐swing outputs, some changes and optimizations have been performed. The use of power‐ground‐free gates in FAs is an important factor to reduce total power consumption [38]. Accordingly, by reducing the static power consumption paths that are usually due to the presence of V DD and GND, dynamic power can also be reduced well.…”

Section: Proposed Circuitsmentioning

confidence: 99%

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Sadeghi

Shiri

Rafiee

et al. 2022

IET Circuits, Devices & Syst

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A new 1-bit full adder (FA) cell illustrating low-power, high-speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process-voltage-temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8-bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing.

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SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Cited by 9 publications

References 53 publications

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

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