2006
DOI: 10.1002/chin.200650219
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Sr2TMO3 (TM: Ni, Co) Compounds with 1D TM—O Chains.

Abstract: Sr 2 TMO 3 (TM: Ni, Co) Compounds with 1D TM-O Chains. -Single-crystalline thin films of the title compounds with a one-dimensional TM-O chain structure are synthesized on a LaSrAlO4 substrate by a pulsed-laser deposition method employing a KrF excimer laser. Buffer layers of Sr2TiO4 and solid solution Sr2(Ti1-xSnx)O4 are used for the growth of Sr2NiO3 and Sr2CoO3 films, respectively. The samples are characterized by XRD, HRTEM, polarized absorption spectroscopy, and third-harmonic generation spectroscopy. Of … Show more

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Cited by 3 publications
(3 citation statements)
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“…Any increase in s/σ beyond 2.8 will result in severe write-ability degradation as I wr reduces significantly. Therefore, s/σ between 2.0 and 2.8 is optimal for balancing the read/write requirements as it results in a maximum SNM and RNM of 145 mV and 245 mV respectively, and maximum I leak of 1 nA along with minimum I wr of 25 µA at V DD = 0.6 V The proposed SNM value ~ 130 mV at 0.6 V is comparable to those published in the literature (122 -172 mV) for DG/Fin FETs [12][13] for a wide range of gate lengths (20 -40 nm). SNM being the most cited SRAM performance metric, should always be compared along with I leak , RNM and I wr to evaluate the optimal design and minimize the read/write trade-offs.…”
Section: T -Sram Cell Designsupporting
confidence: 59%
“…Any increase in s/σ beyond 2.8 will result in severe write-ability degradation as I wr reduces significantly. Therefore, s/σ between 2.0 and 2.8 is optimal for balancing the read/write requirements as it results in a maximum SNM and RNM of 145 mV and 245 mV respectively, and maximum I leak of 1 nA along with minimum I wr of 25 µA at V DD = 0.6 V The proposed SNM value ~ 130 mV at 0.6 V is comparable to those published in the literature (122 -172 mV) for DG/Fin FETs [12][13] for a wide range of gate lengths (20 -40 nm). SNM being the most cited SRAM performance metric, should always be compared along with I leak , RNM and I wr to evaluate the optimal design and minimize the read/write trade-offs.…”
Section: T -Sram Cell Designsupporting
confidence: 59%
“…Lg (nm) Also, fin height tuning is possible in a Bulk-Si FinFET (5). It is easy to adjust fin height by controlling SiO 2 recess thickness while fin height of SOI-FinFET is decided by SOI layer thickness at the very early stage of the process.…”
Section: (B))(4)mentioning
confidence: 99%
“…Especially, SRAM cell uses the smallest transistors and it suffered from the severe degradation in the stability. Therefore, many studies have been focusing on the FinFET SRAM technology to aggressively scale the SRAM cell while maintaining good circuit performance [3].…”
Section: Introductionmentioning
confidence: 99%