FinFETs with either a Bulk-Si and a SOI substrate are broadly believed to be promising device structures for 22 nm node and beyond since they have superior short channel immunity and less performance variability. There are, however, concerns in integrating FinFETs, which can meet requirements from the viewpoints of manufacturability and performance. This paper will review the key FinFET process technologies for fabrication of sub-15 nm FinFET and reduction of its parasitic resistance.