SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview

Abstract

Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.

In-Memory Principal Component Analysis by Analogue Closed-Loop Eigendecomposition

“…8a, 10 kΩ LRS, 4F 2 cell area, 5 ns write time, 0.5 pJ programming energy [16], 10% programming variability [17]) or a 4T4R-CMOS technology (Fig. 8b, 5 kΩ LRS, 10 µm 2 cell area, 33 ps write time, 4 fJ programming energy [18], negligible variability). ...…”

From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects

“…Diving into memory and Artificial Intelligence (AI) realms, the paper by Gul et al introduces the idea of compute-in-memory (CIM) as an innovative solution to address data traffic challenges in AI systems employing deep neural networks (DNNs) [9]. Notably, FinFET-based 6T-SRAM cells are emphasized for their fit in CIM architectures, marking a significant transition from planar transistors to the advanced 3D-FinFET structure.…”

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

“…The 6T-SRAM cell has evolved in parallel to transistor evolution by adopting evolved structural modifications in the transistor. extra control signals, and cell area [74]. However, the FinFET 6T-SRAM differs in transistor structure from the planar CMOS.…”

“…Conventional 6T-SRAM cells ( Figure 4 ) are still an appealing choice for cache memory mass production due to the minimum number of transistors, dual port for read and write operations, and less leakage current as compared with 7T and 8T SRAM cells. Alternate cells have an edge in noise margins, internal node isolation, and half-cell selection issues but at the expense of increased peripheral circuits, operational complexity, extra control signals, and cell area [ 74 ]. However, the FinFET 6T-SRAM differs in transistor structure from the planar CMOS.…”