SRAM failure analysis evolution driven by technology scaling

Song, Zhigang

doi:10.1109/ipfa.2014.6898207

Cited by 8 publications

(3 citation statements)

References 20 publications

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“…In general, FA is fulfilled by conventional Physical Failure Analysis (PFA) techniques such as Passive Voltage Contrast (PVC), Scanning Electron Microscope (SEM), Focused Ion Beam (FIB), and Transmission Electron Microscope (TEM) [6][7]. However, traditional PFA takes long time to identify defects and limited failures could be analyzed.…”

Section: Introductionmentioning

confidence: 99%

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

Kim

et al. 2021

International Symposium for Testing and Failure Analysis

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Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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Section: Introductionmentioning

confidence: 99%

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

Kim

et al. 2021

International Symposium for Testing and Failure Analysis

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“…Semiconductor technology is continuously shrinking because of the demand for high speed and more function microelectronic devices. Static Random Access Memory (SRAM), which serve as caches in microprocessor or System on Chip (SoC) device occupies up to 90% of chip area [1][2], and adopts even more aggressive design rule than logic circuitry in the same technology generation. In addition, it is becoming denser and smaller in size by continuous scaling of critical dimensions with the new process technology development.…”

Section: Introductionmentioning

confidence: 99%

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

Kim

2021

International Symposium for Testing and Failure Analysis

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As technology scales down, the density of Static Random Access Memory (SRAM) devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node. In addition, resistive defects and parametric defects are increasing which are hard to detect by the conventional test. Thus, the need of effective tests with high fault coverage and low cost increases. In this work, we study the reuse of assist technique (read and write assist) and timing margin control technique, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of hard-to-detect marginal defects. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits and timing control circuits can be leveraged to increase the defect coverage can be increases up to 28% at nominal operation voltage by simulation. Some successful case studies are also discussed to demonstrate the efficiency of the proposed electrical stress test methodology.

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“…In nonvolatile memory (NVM) devices, the memory bit-counting is even more challenging, since the metal layer (here it is M5) blocking the WLs directly lands on the memory cells (Figure 2a, b). There have been numerous FA studies on SRAM/NVM devices, from hard short/open failure [2][3][4] to subtle defect induced marginal failure [5][6][7]. After the electrical fault isolation (EFI) or bit-map analysis, memory bit-counting is the key step for TEM analysis or transistor-level probing to locate the defect.…”

Section: Introductionmentioning

confidence: 99%

Laser Deprocessing Technique and its Application to Physical Failure Analysis

Pan¹,

Thong²,

Tan³

et al. 2020

Adv. sci. technol. eng. syst. j.

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This paper is an extension of work originally presented in IPFA 2019. In the original work, a new memory bit-counting method in physical failure analysis (PFA) using laser deprocessing technique (LDT) is introduced. In the present paper, LDT will be further exploited and the methodology applied to PFA will be fully discussed. Compared to the conventional methods that involve high-cost equipment such as focused ion beam (FIB) and reactive ion etcher (RIE), the novel LDT method using a laser system instead lowers the cost by more than 5 times and shortens the failure analysis (FA) cycle time by up to 45%. The new improved methodology can significantly increase PFA throughput especially in semiconductor foundries, and facilitate more applications in other types of FA labs.

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SRAM failure analysis evolution driven by technology scaling

Cited by 8 publications

References 20 publications

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

Advanced Soft Defect Screen Methodology for Nanoscale SRAM Yield Improvement

Laser Deprocessing Technique and its Application to Physical Failure Analysis

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