SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Mukhopadhyay, Saibal; Rao, Rahul; Kim, Jae‐Joon; Chuang, Ching-Te

doi:10.1109/tvlsi.2009.2029114

Cited by 70 publications

(38 citation statements)

References 13 publications

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“…The process variation in high frequency operation increases Tdischar g e beyond the word-line activation period (TlI'f) which leads to a write-failure. For a successful write operation the summation of Tdischarge and Tfalchll p should be at most the TlI'f [2]. Fig.…”

Section: A Write Ability Enhancement Of Cc-sram Cellmentioning

confidence: 99%

Power efficient design of a novel SRAM cell with higher write ability

Nayak

Acharya

Mahapatra

2015

2015 Annual IEEE India Conference (INDICON)

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The modern high-performance portable communication devices are the key to make the world more inclusive than before. There is a great demand for high performance SOC inside the high-performance portable devices.According to ITRS and current research, on chip memory technology plays a great role in the SOC performance. Hence enhancing on-chip memory performance will lead to performance enhancement of the device. A novel SRAM cell is designed which reduces the total power consumption by 15.33%. It also increases the write-ability by 63.61% with respect to the conventional 6T-SRAM cell. It blocks the short circuit current during state transition to reduce the dynamic power consumption. During a write operation, it initiates the feedback loop process for data latching, earlier than the 6T SRAM cell which increases the write-ability of the proposed cell by a large amount. A thorough analysis about power consumption, write-ability and physical layout design of the proposed cell array is carried out and compared with that of a conventional 6T -SRAM cell array.

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Section: A Write Ability Enhancement Of Cc-sram Cellmentioning

confidence: 99%

Power efficient design of a novel SRAM cell with higher write ability

Nayak

Acharya

Mahapatra

2015

2015 Annual IEEE India Conference (INDICON)

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“…WL undergoes similar transition as WE, which connects the storing node Q to the negatively biased bitline and causes voltage at node Q to discharge faster due to increased strength of access transistor and thus, providing a faster write operation. NBL technique tends to provide better Write Margin (WM) than suppressed cell supply technique [10]. When SSS is combined with NBL scheme, a further better write performance is achieved.…”

Section: A Proposed Sss Assist Circuitmentioning

confidence: 99%

“…after time instant T 0 . The behavior of bit-line BL for entire write duration can be mathematically represented by equation (1) and (2) [10].…”

Section: Analytical Modeling Of Sss-nblmentioning

confidence: 99%

“…Impact of different assist circuits on SRAM beyond 22nm technology node is presented in [9]. In row-based WA, read failure probability for half selected cells along the selected row is greater than column based WA techniques [10]. Column-based Transient NBL voltage generation using capacitive coupling is reported in [10] which is sensitive to arrival time of BIT EN signal.…”

Section: Introductionmentioning

confidence: 99%

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Operation-aware assist circuit design for improved write performance of FinFET based SRAM

Prajapati

Yadav

Pattanaik

et al. 2014

18th International Symposium on VLSI Design and Test

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Aggressively scaled SRAM is highly vulnerable to short channel and process variation effects. FinFET technology emerges as a device level solution to overcome these scaling limitations while assist techniques aid super-scaled SRAM to achieve better performance and stability. In this paper, we propose two operation-aware assist circuits, namely, Split and Suppressed cell Supply (SSS) and Negative Bit-Line scheme incorporated SSS (SSS-NBL) to provide better write performance without compromising read performance. We exploit cell supply collapse scheme in SSS to achieve low power consumption and improved write performance whereas SSS-NBL further ameliorates write performance. A new analytical model is derived for SSS-NBL. Simulation results reflect an improvement of 0.53% in read performance of 6T SRAM cell whereas 34.02% and 27.86% in write performance using SSS for 6T and PPN-based 10T SRAM cell, respectively. Similarly, SSS-NBL offers 37% and 32.63% improved write performance over 6T and PPN-based 10T bitcell, respectively.

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“…The half accessed cells are the ones that share the same row with the one undergoing the write operation and for these cells the word-line is asserted but the bit-lines are not pulled low [4]. Word line (WL) boosting has been proven to be the most efficient write-assist technique [4], [5] while increasing the array's supply voltage is the most efficient read-assist technique [8]. In this work several assist techniques for SRAM cell functionality improvement have been analyzed.…”

Section: Introductionmentioning

confidence: 99%

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

Vatajelu

Figueras

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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The efficiency of different assist techniques for SRAM cell functionality improvement under the influence of random process variation is studied in this paper. The sensitivity of an SRAM cell functionality metrics when using control voltage level assist techniques is analyzed in read and write operation modes. The efficiency of the assist techniques is estimated by means of parametric analysis. The purpose is to find the degree of functionality metric improvement in each operation mode. The Acceptance Region concept is used for parametric analysis of SRAM cell functionality under random threshold voltage variations. In order to increase the reliability of the SRAM several assist techniques, chosen among the most efficient ones for each operation mode, are considered. This analysis offers a qualitative indication of the cell's functionality improvement by means of the efficient computation of a metric in parameter domain analysis. The results are proven to have high correlation with the ones obtained by means of the classical Monte Carlo simulations with significant savings in comparing different assist techniques.

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SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

Cited by 70 publications

References 13 publications

Power efficient design of a novel SRAM cell with higher write ability

Power efficient design of a novel SRAM cell with higher write ability

Operation-aware assist circuit design for improved write performance of FinFET based SRAM

Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation

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