2016 26th International Conference on Field Programmable Logic and Applications (FPL) 2016
DOI: 10.1109/fpl.2016.7577363
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SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA

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Cited by 4 publications
(2 citation statements)
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“…However, GPU acceleration approach is very power consuming, and some robots, like a hover, may not be allowed to carry a GPU hosted in a PC or notebook computer. Other acceleration approaches are based on FPGA or ASIC have been proposed [12][13][14][15]. The design that implements SURF detection and description achieves a speed performance of 72FPS on Stratix III @1080P [14].…”
Section: Introductionmentioning
confidence: 99%
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“…However, GPU acceleration approach is very power consuming, and some robots, like a hover, may not be allowed to carry a GPU hosted in a PC or notebook computer. Other acceleration approaches are based on FPGA or ASIC have been proposed [12][13][14][15]. The design that implements SURF detection and description achieves a speed performance of 72FPS on Stratix III @1080P [14].…”
Section: Introductionmentioning
confidence: 99%
“…Other acceleration approaches are based on FPGA or ASIC have been proposed [12][13][14][15]. The design that implements SURF detection and description achieves a speed performance of 72FPS on Stratix III @1080P [14]. In [16], a complete hardware acceleration system which include FAST feature point detection, BRIEF description and matching reaches 308FPS on Zynq @640  480.But robustness of FAST feature points is weaker than that of SURF.…”
Section: Introductionmentioning
confidence: 99%