SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs

Liu, Qi; Sun, Mo; Sun, Jie; Lu, Liqiang; Zhao, Jieru; Wang, Zeke

doi:10.1109/icfpt59805.2023.00023

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2024

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Cited by 3 publications

References 28 publications

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Hybrid Processing Unit for Efficient Realization of DNN on FPGA Devices

Devi Paladi,

Rani Thuraka

2024

2023 Second IEEE International Conference on Measurement, Instrumentation, Control and Automation (ICMICA)

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Hybrid Processing Unit for Efficient Realization of DNN on FPGA Devices

Devi Paladi,

Rani Thuraka

2024

2023 Second IEEE International Conference on Measurement, Instrumentation, Control and Automation (ICMICA)

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FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs

Lou,

Qin,

Wang

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators

Brignone,

Bosio,

Ottati

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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High-level synthesis (HLS) aims at democratizing custom hardware acceleration with highly abstracted software-like descriptions. However, efficient accelerators still require substantial low-level hardware optimizations, defeating the HLS intent. In the context of field-programmable gate arrays, digital signal processors (DSPs) are a crucial resource that typically requires a significant optimization effort for its efficient utilization, especially when used for sub-word vectorization. This work proposes SILVIA, an open-source LLVM transformation pass that automatically identifies superword-level parallelism within an HLS design and exploits it by packing multiple operations, such as additions, multiplications, and multiply-and-adds, into a single DSP. SILVIA is integrated in the flow of the commercial AMD Vitis HLS tool and proves its effectiveness by packing multiple operations on the DSPs without any manual source-code modifications on several diverse state-of-the-art HLS designs such as convolutional neural networks and basic linear algebra subprograms accelerators, reducing the DSP utilization for additions by 70 % and for multiplications and multiply-and-adds by 50 % on average.

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SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs

Cited by 3 publications

References 28 publications

Hybrid Processing Unit for Efficient Realization of DNN on FPGA Devices

Hybrid Processing Unit for Efficient Realization of DNN on FPGA Devices

FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs

SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators

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