A field programmable gate array (FPGA) based model predictive controller for two phases of spacecraft rendezvous is presented. Linear time-varying prediction models are used to accommodate elliptical orbits, and a variable prediction horizon is used to facilitate finite time completion of the longer range manoeuvres, whilst a fixed and receding prediction horizon is used for fine-grained tracking at close range. The resulting constrained optimisation problems are solved using a primal-dual interior point algorithm. The majority of the computational demand is in solving a system of simultaneous linear equations at each iteration of this algorithm. To accelerate these operations, a custom circuit is implemented, using a combination of Mathworks HDL Coder and Xilinx System Generator for DSP, and used as a peripheral to a MicroBlaze softcore processor on the FPGA, on which the remainder of the system is implemented. Certain logic that can be hard-coded for fixed sized problems is implemented to be configurable online, in order to accommodate the varying problem sizes associated with the variable prediction horizon. The system is demonstrated in closed-loop by linking the FPGA with a simulation of the spacecraft dynamics running in Simulink on a PC, using Ethernet. Timing comparisons indicate that the custom implementation is substantially faster than pure embedded software-based interior point methods running on the same MicroBlaze and could be competitive with a pure custom hardware implementation.During the impulsive phase, the control objective is to guide the chaser towards the vicinity of the target via a sequence of predetermined 'holding points' at which it must remain pending clearance to continue (Figure 1(b)). Such trajectories are often informally described as hopping, because in the ideal case (without any parametric or additive uncertainties), they comprise impulsive inputs at the start and finish separated by a long period of free drift. In the present scenario, the holding Recently, interest has arisen in using FPGAs to exploit opportunities for parallelism in the numerical algorithms used to implement MPC, with a variety of approaches proposed. A hybrid softwarehardware design is advocated by [32][33][34]. The first uses a primal barrier method, and the custom accelerator is used to calculate the gradient vector and Hessian matrix of the augmented cost function at each iteration, whilst the latter two use an active set method, with a custom circuit expediting At a high level, the custom PCORE is split into two major parts. The first component performs steps 6-8 and 10 of the Algorithm in Figure 2(a), building the linear system, whilst the second more complex component performs step 9.