Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations

Hangmann, Christian; Hedayat, Christian; Hilleringmann, Ulrich

doi:10.1109/tcsi.2014.2333331

Cited by 10 publications

(5 citation statements)

References 9 publications

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“…3 [14], [21]. To simulate the dynamics of the CP-PLL, a set of state variables characterizing the ED model are defined.…”

Section: Event-driven Based Design Approachmentioning

confidence: 99%

“…Additionally, the validity of these modeling approaches is limited to the domain close to the operation point, discarding them for transient pull-in predictions which are essential when considering frequency synthesis. They cannot characterize the complex system properties like switching, pull-in process and chaotic behavior [14]. Design tools based on SystemC and SystemC-AMS [15] combine the system level representation with the circuit level.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Guerin,

Haddad,

Sazzad

et al. 2023

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

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“…3 [14], [21]. To simulate the dynamics of the CP-PLL, a set of state variables characterizing the ED model are defined.…”

Section: Event-driven Based Design Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Guerin,

Haddad,

Sazzad

et al. 2023

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…The accuracy of the frequency, phase, and pulse width of the clock signal is important for circuit applications. However, the phase locked loop (PLL) [1][2][3] or delay locked loop (DLL) [4,5], can only correct the signal frequency and phase. A clock with a 50% duty cycle is very important in many applications, such as double data rate synchronous dynamic random access memory (DDR-SDRAM) and double-sampling analog-to-digital converters (ADC).…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency

Kao

2021

Electronics

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This paper presents a fast locking and wide range input frequency all-digital duty cycle corrector (ADDCC). The proposed ADDCC circuit comprises a pulse generator and a clock generator. The pulse generator is edge-triggered by an input signal to produce a 0 degree and 180 degree phase. The clock generator uses a 0 degree and 180 degree phase to produce the 50% duty cycle output signal. It corrects the duty cycle of the input signal in six clock cycles. The proposed ADDCC is implemented in a 0.35 µm CMOS process. The circuit can operate from 10 MHz to 100 MHz, and accommodates a wide range of input duty cycles ranging from 30% to 70%. The duty-cycle error of the output signal is less than ±1%.

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“…In order to suppress the ripple, decreasing the loop bandwidth is an effective way [14,15]. Besides, many other attempts have also been tried to reduce reference spur in the past few years [16,17,18,19,20,21,22,23,24,25]. For example, a PLL with randomly selected PFD is described to average the charge pump output ripple, in which four PFDs operating at different frequencies are exploited [20].…”

Section: Introductionmentioning

confidence: 99%

A low reference spur phase-locked loop realized with dynamic current injection charge pump

2019

IEICE Electron. Express

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A dynamic current injection charge pump (DCI-CP) is proposed to obtain perfect dynamic current match in this paper. In the proposed DCI-CP, dynamic injection current which includes positive injection current and negative injection current is generated to compensate the dynamic current mismatch. To verify the proposed DCI-CP, a CPPLL is fabricated in SMIC 0.18-µm CMOS process. Measurement results show that it synthesizes frequency from 0.6 to 1.3 GHz with a supply voltage of 1.8 V, consuming 4.7 mW. Simulation results show the dynamic current mismatching of proposed DCI-CP is as low as 4 nA even in the worst case. The measurement reference spur achieves −74 dBc at 1.1 GHz oscillation frequency, of which the maximum and minimum reduction are 9 dB and 3 dB, respectively. The phase noise achieves −98.5 dBc/Hz @1 MHz offset. The core occupies a die area of 0.154 mm 2 totally.

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Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations

Cited by 10 publications

References 9 publications

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Design and Implementation of Fast Locking All-Digital Duty Cycle Corrector Circuit with Wide Range Input Frequency

A low reference spur phase-locked loop realized with dynamic current injection charge pump

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