2001
DOI: 10.1116/1.1387464
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Stability of cerium oxide on silicon studied by x-ray photoelectron spectroscopy

Abstract: The silicon-cerium oxide interface is studied using x-ray photoelectron spectroscopy. The oxidation and reduction of species at the interface are examined as a function of annealing temperature both in vacuum and oxygen ambient, in order to determine their relative stabilities. By depositing a very thin CeO 2 film ͑ϳ30 Å͒, the cerium and silicon core level peaks can be monitored simultaneously. The presence of characteristic chemical shifts of the Si 2p peak gives information about any SiO x layer that may for… Show more

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Cited by 132 publications
(103 citation statements)
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“…However, growth 5,8,9 of high-quality ultrathin films, which is crucial for optimized integration, has so far been considerably impeded by Ce-promoted Si oxidation at the interface, resulting in subsequent silicon oxide and cerium silicate formation. [10][11][12] Yet, despite its higher lattice mismatch of about 2.7% using two silicon lattice constants as reference, 13 cubic Ce 2 O 3 is generally believed to be well suited as a buffer layer for sequential CeO 2 deposition due to its lower oxidation state, potentially avoiding the concomitant evolution of SiO x and CeSi x O y species. These low-k defect phases give rise to significant interfacial charge trapping while lowering the dielectric constant of the film and increasing the effective oxide thickness (EOT) of the metal insulator semiconductor field-effect transistor (MISFET) structure.…”
Section: Introductionmentioning
confidence: 99%
“…However, growth 5,8,9 of high-quality ultrathin films, which is crucial for optimized integration, has so far been considerably impeded by Ce-promoted Si oxidation at the interface, resulting in subsequent silicon oxide and cerium silicate formation. [10][11][12] Yet, despite its higher lattice mismatch of about 2.7% using two silicon lattice constants as reference, 13 cubic Ce 2 O 3 is generally believed to be well suited as a buffer layer for sequential CeO 2 deposition due to its lower oxidation state, potentially avoiding the concomitant evolution of SiO x and CeSi x O y species. These low-k defect phases give rise to significant interfacial charge trapping while lowering the dielectric constant of the film and increasing the effective oxide thickness (EOT) of the metal insulator semiconductor field-effect transistor (MISFET) structure.…”
Section: Introductionmentioning
confidence: 99%
“…This indicates that the ceria sample underwent a partial reduction in state from Ce 4þ to Ce 3þ in UHV, which is consistent with observations of Zhang et al 55 Specifically, it can be seen in Figures 2(a) and 2(b) that the intensity of both the characteristic Ce 3þ peaks v 0 and u 0 increased following overnight relaxation in UHV, while the characteristic Ce 4þ peaks v, v 00 , v 000 , u, u 00 , and u 000 all decreased in intensity. Preisler et al 57 have further correlated the change in the oxidation state from Ce 4þ to Ce 3þ with a net decrease in the O/Ce ratio. Therefore, in view of all these observations, we can say, that the change in cerium chemistry, as seen in Figures 2(a) and 2(b), is consistent with the hypothesis that surface relaxation in UHV caused an overall decrease in the surface O/Ce ratio.…”
mentioning
confidence: 99%
“…The thickness of the ALD oxide is affirmed by using attenuation equations of the substrate peak using the XPS. [17,18] The relaxation energies are determined by assuming them to be half the Auger parameter shifts. [19] The auger parameters are calculated from the oxygen O1s core-level and the OKL 1 L 1 auger peak of the SiO 2 with different thicknesses.…”
Section: Resultsmentioning
confidence: 99%