“…However, this approach incurs area and power overhead. To reduce the V OS while minimizing the area and power overhead, various offset reducing circuit techniques have been proposed [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 ]. This paper aims to conduct a comparative analysis of these circuits, explaining their effectiveness in reducing the V OS and achieving power and performance benefits.…”