Stacking fault expansion from basal plane dislocations converted into threading edge dislocations in 4H-SiC epilayers under high current stress

Abstract

We evaluate the stacking faults (SFs) expansion from basal plane dislocations (BPDs) converted into threading edge dislocations (TEDs) under the current stress to the pn devices and analyzed the nucleation site of the SF by combined polishing, chemical etching in molten KOH, photoluminescence imaging, Focus ion beam, transmission electron microscopy, and Time-of-Flight secondary ion mass spectrometer techniques. It was found that the formation of SFs occurs upon the current stress levels of 400 A/cm2 where the diode area is not including BPDs in the drift layer after the high current stress, and the high current stress increases the SFs expansion density. It was also found the dependence of the junction temperature. The estimated activation energy for the expansion of SFs is Ea = 0.46 eV. The SF extends from the conversion point of the BPD into the TED within buffer layer. Even though BPDs converted into TEDs within the high doped buffer layer, SFs expand under high current stress.

Origin and Generation Process of a Triangular Single Shockley Stacking Fault Expanding from the Surface Side in 4H-SiC PIN Diodes

“…The 1SSFs of T1 and T3 had a right-angled corner on the right side, and these two types are the most frequently observed and repo rted. 3,[5][6][7][9][10][11][12][13][14]16,[19][20][21][22] However, the 1SSFs of T2 had a triangular shape with a right-and-left in contrast to T1 and T3. The expansion direction of T2, which was from the surface to the substrate/epilayer interface, was opposite to that of T3.…”

“…4 Most previous studies on the expansion of 1SSFs have found that the SSFs originate from two kinds of BPDs: one that had penetrated from the substrate into the epilayer, 5,6 and another that had converted to a threading edge dislocation (TED) around the substrate/epilayer interface during epitaxial growth. 7 In addition, many analyses have been conducted of these 1SSFs, including current/temperature stress testing, [8][9][10][11][12][13][14] calculations, [15][16][17][18] and crystal analysis. [19][20][21][22][23] The BPD detection by photoluminescence (PL) imaging and the use of a buffer layer between the substrate and the epitaxial layer was proposed as a method for controlling 1SSF expansion 4,7,11,24 with the aim of solving the V F degradation issue.…”

Silicon carbide power electronics for electric vehicles

“…They include micropipes, carrots, triangular defects, threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) in SiC bulk substrates and epitaxial layers. High power semiconductor device quality was degraded under the forward bias conditions due to the presence of such defects because electron-hole recombination introduces stacking faults leading to an increase in the voltage drop [18]. This resulted in a significant decrease in the operational lifetime and deviations in device characteristics.…”

“…In the case of BPD concentration, the most common solution is to turn these defects located in substrates into TEDs located at the substrate/epitaxial layer interface. This can be achieved by different techniques such as modification of epitaxial growth conditions like the carbon/silicon ratio and temperature [18].…”

Effect of Various Defects on 4H-SiC Schottky Diode Performance and Its Relation to Epitaxial Growth Conditions

“…and deep level defects, etc. [7][8][9][10][11][12][13][14][15], which will inevitably have a serious impact on the performance of 4H-SiC power devices and ultraviolet photodetectors. Among the morphological defects, micropipes have serious impact on the device performance but are preventable, since the substrates with micropipe density less than 0.1 cm −2 are commercially available [16][17][18].…”