Stacking of known good rebuilt wafers with Through Polymer Via based 3D interconnect application to high speed DDR3

Noiray, J.; Val, C.; Couderc, Pascal

doi:10.1109/eptc.2012.6507121

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC) 2012

DOI: 10.1109/eptc.2012.6507121

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Stacking of known good rebuilt wafers with Through Polymer Via based 3D interconnect application to high speed DDR3

J. Noiray¹,

C. Val²,

Pascal Couderc³

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Stacking of known good rebuilt wafers for high performance memory and SiP

Couderc¹,

Noiray²,

Val³

2013

International Symposium on Microelectronics

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Based on Wire-free Die on Die disruptive technology (WDoD™), high density memory can be manufactured in a small form factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Dual die (DD) and Quad die (QD) DDR3 memories exhibit outstanding performance and show the path to highly densified System in Package (SiP) for Medical, Defense and Industrial markets

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Stacking of known good rebuilt wafers for high performance memory and SiP

Couderc¹,

Noiray²,

Val³

2013

International Symposium on Microelectronics

View full text Add to dashboard Cite

show abstract

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Stacking of known good rebuilt wafers with Through Polymer Via based 3D interconnect application to high speed DDR3

Cited by 1 publication

References 1 publication

Stacking of known good rebuilt wafers for high performance memory and SiP

Stacking of known good rebuilt wafers for high performance memory and SiP

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