Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Cho, Chang-Burm; Zhang, Wangyuan; Li, Tao

doi:10.1109/micro.2007.21

Cited by 289 publications

(171 citation statements)

References 21 publications

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“…QoS-aware memory controllers were proposed in various contexts including a packet memory environment [1] and multi-processor environments [2,3,4,5]. In [1], the proposed adaptive feedback mechanism dynamically adjusts allocated bandwidths to different classes based on latency violations.…”

Section: Related Workmentioning

confidence: 99%

“…In [1], the proposed adaptive feedback mechanism dynamically adjusts allocated bandwidths to different classes based on latency violations. In [2,3], a fair queueing method is employed to allocate bandwidth for different processor threads whereas in [4,5], priority scheduling is used to schedule threads based on their sensitivity to inter-thread interference, latency, or bandwidth.…”

Section: Related Workmentioning

confidence: 99%

“…However, the methods proposed for multi-processor environment in [2,3,4,5] are not adequate for the packet memory because data mapping on DRAM and data access patterns in the packet memory are different than those in the multi-processor environment. In [4,5], they provide high priority to the threads with latency sensitivity.…”

Section: Related Workmentioning

confidence: 99%

“…In [4,5], they provide high priority to the threads with latency sensitivity. However, priority scheduling cannot simultaneously meet latency requirements of multiple classes even under non-overload cases.…”

Section: Related Workmentioning

confidence: 99%

“…and solving these n equations gives the weight for each class 4 For the cases where there are more traffics than the scheduler can handle, the proposed scheme assigns a high priority class the bandwidth needed to fulfill its requirement and assigns the remaining bandwidth to the rest. Fig.…”

Section: Calculating Bandwidth and Weight For Each Classmentioning

confidence: 99%

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Design of a bitmap-based QoS-aware memory controller for a packet memory

Yoon

Chung

et al. 2014

IEICE Electron. Express

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Abstract:A packet memory controller in routers accesses the packet memory according to the QoS requirements of packets. The previous QoS-aware controller using a feedback control loop degenerates into round robin scheduling under temporary overload and suffers from slow response. We propose a new packet memory controller that estimates input load accurately and rapidly and schedules different classes using a flexible bitmap scheduler. The results show that under temporary overload or rapidly changing input loads, it can successfully meet the latency requirements by showing only less than 2% difference from the requirement of the high priority class.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Calculating Bandwidth and Weight For Each Classmentioning

confidence: 99%

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Design of a bitmap-based QoS-aware memory controller for a packet memory

Yoon

Chung

et al. 2014

IEICE Electron. Express

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WinDRAM: Weak rows as in‐DRAM cache

Kumar

Sinha

Das

2022

Concurrency and Computation

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The primary factor responsible for increasing the refresh rate is the presence of weak rows in a DRAM. They have a shorter retention time and lose charge faster than regular rows. Recently, a technique known as in-DRAM cache was introduced in which some DRAM rows act as a separate module. The in-DRAM cache can be used for a variety of purposes in DRAM. We present WinDRAM, an in-DRAM cache comprised of all the DRAM's weak rows. The most recently accessed rows are copied into the in-DRAM cache so that when the row is accessed again, both rows (original and copy) can be activated at the same time. Such simultaneous activation reduces activation time and, as a result, DRAM access latency. Dual-row activation is the term for this concept. Because weak rows are part of the in-DRAM cache and are frequently accessed, WinDRAM does not perform a periodic refresh on them. Existing techniques based on in-DRAM cache do not design the in-DRAM cache using weak rows. WinDRAM proposes a novel idea by designing the in-DRAM cache using weak rows. Because the weak rows do not need to be refreshed, the refresh interval of the remaining rows can be increased, resulting in a refresh rate reduction of 80% to 90%. The speedup is 15% to 25% faster than standard DRAM and 12.77% faster than previous work for high memory-intensive workloads. Overall energy consumption is also reduced by 10% to 15%. K E Y W O R D SDRAM refresh, dual-row activation, in-DRAM cache, weak row INTRODUCTIONModern, high-performance computers require both on-chip and off-chip memory designs that are efficient. As the number of cores in modern multi-core systems increases, the need for bigger and more efficient main memory becomes crucial. With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases. 1 However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory. 1 Due to its improved density and capacity as well as its low production costs, DRAM has become the primary component of most contemporary main memories. 2,3 Typically, a DRAM bank is partitioned into many subarrays, as described in Section 2.Each subarray stores several DRAM cells in a 2D fashion (having rows and columns). Each DRAM cell is responsible for storing a single bit of data.The capacitor included within the cell stores the bit as a charge. For instance, a completely charged capacitor indicates that the cell contains bit 1.However, DRAM cells are leaky and lose their charge over a period of time (retention time). To keep the data contained within these cells, periodic refresh procedures must be done. Due to the recent increase in memory-intensive applications, the DRAM is being increased to meet their requirements. Consequently, the energy required to retain the data in the DRAM cells via periodic refresh increases essentially with the size of the main memory. 1 Refresh activities in a DRAM are accountable for up to fifty percent of the DRAM's power consumption. 4,5 In addition, these opera...

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Main Memory Scaling: Challenges and Solution Directions

Mutlu

2015

More Than Moore Technologies for Next Generation Computer Design

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The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques.In this chapter, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we describe three major solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system (an approach we call system-DRAM co-design), 2) designing a memory system that employs emerging non-volatile memory technologies and takes advantage of multiple different technologies (i.e., hybrid memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems). We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory. IntroductionMain memory is a critical component of all computing systems, employed in server, embedded, desktop, mobile and sensor environments. Memory capacity, energy, cost, performance, and management algorithms must scale as we scale the size of the computing system in order to maintain performance growth and enable new applications. Unfortunately, such scaling has become difficult because recent trends in systems, applications, and technology greatly exacerbate the memory system bottleneck.v

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Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

Cited by 289 publications

References 21 publications

Design of a bitmap-based QoS-aware memory controller for a packet memory

Design of a bitmap-based QoS-aware memory controller for a packet memory

WinDRAM: Weak rows as in‐DRAM cache

Main Memory Scaling: Challenges and Solution Directions

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