Standard Cell-Based Ultra-Compact DACs in 40-nm CMOS

Abstract

In this paper, very compact, standard cell-based Digital-to-Analog converters (DACs) based on the Dyadic Digital Pulse Modulation (DDPM) are presented. As fundamental contribution, an optimal sampling condition is analytically derived to enhance DDPM conversion with inherent suppression of spurious harmonics. Operation under such optimal condition is experimentally demonstrated to assure resolution up to 16 bits, with 9.4-239X area reduction compared to prior art. The digital nature of the circuits also allows extremely low design effort in the order of 10 man-hours, portability across CMOS generations, and operation at the lowest supply voltage reported to date. The limitations of DDPM converters, the benefits of the optimal sampling condition and digital calibration were explored through the optimized design and the experimental characterization of two DACs with moderate and high resolution. The first is a general-purpose DAC for baseband signals achieving 12-bit (11.6 ENOB) resolution at 110kS/s sample rate and consuming 50.8µW, the second is a DAC for DC calibration achieving 16-bit resolution with 3.1-LSB INL, 2.5-LSB DNL, 45µW power, at only 530µm 2 area.INDEX TERMS Digital to analog converter (DAC), automated design, calibration, fully synthesizable, fully digital, ultra-low design effort, standard-cell-based analog circuits.

Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

“…The table shows that the proposed ADC architecture exhibits the smallest area normalized to F 2 , as needed to fairly compare to other demonstrations regardless of the adopted technology. In particular, the proposed ADC architecture occupies 12-95x less area than Flash ADCs [6]- [8], and 1.4x less normalized area than the very compact SAR architecture in [9]. The proposed ADC architecture also achieves the highest effective resolution of 6.4 bits across fully-synthesized ADCs reported to date, as well as the best performance in term of SNDR and SFDR (i.e., resolution).…”

“…In this case, such circuits can be straightforwardly integrated with an existing library by The input voltage v IN is applied to one of the two inputs of the AMUX. The other input is connected to the output of a Dyadic Digital Pulse Modulator (DDPM) [7], [8], [19], which provides a digital stream with a pulse density n/2 N over a 2 N clock cycles as illustrated in Fig. 2…”

“…In turn, the DAC input word is provided by the successive approximation register (SAR) logic to progressively approach the input voltage v IN , as detailed in the following. Detailed structure of the output sequences generated by a DDPM modulator [7], [8], [19] (example with N = 3 bit).…”

Design and implementation of 4 bit binary weighted current steering DAC

“…Thermometer code is used to control the switches. Additional hardware is required to convert binary code into thermometer codes [26][27][28][29].…”

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

“…An alternative approach [17][18][19][20][21][22][23][24][25][26][27] aims at the implementation of analog functions by digital means. Leveraging this concept, a VCO-based OTA [28] and a digital-based [15] OTA (DB-OTA), Figure 1f,g, have been recently proposed [13,16].…”