Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

Abstract

The practicability and methodology of applying resolutionenhancement-technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from Ϫ4.2 to Ϫ15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from Ϫ16.2 to ϩ2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Photo-Optical Instrumentation Engineers.