STARPro — A new multithreaded direct execution platform for Esterel

Yuan, Simon; Andalam, Sidharta; Yoong, Li Hsien; Roop, Partha S.; Salčić, Zoran

doi:10.1016/j.entcs.2008.01.005

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…The first reactive processor, called REFLIX, was designed by Salcic et al [2002], followed by a number of follow-up designs [Yuan et al 2009]. This concept of reactive processors was then adapted to PRET-C with the ARPRET platform (Auckland Reactive PRET).…”

Section: Instruction Set Architectures For Synchronous Programmingmentioning

confidence: 99%

Building timing predictable embedded systems

Axer

Ernst

Falk³

et al. 2014

ACM Trans. Embed. Comput. Syst.

101

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A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

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Section: Instruction Set Architectures For Synchronous Programmingmentioning

confidence: 99%

Building timing predictable embedded systems

Axer

Ernst

Falk³

et al. 2014

ACM Trans. Embed. Comput. Syst.

101

View full text Add to dashboard Cite

show abstract

“…To guarantee predictability, all instructions and data are stored in on-chip memory. Any read/write operation takes only one clock cycle, simplifying the problem of PFU is inspired by the STARPro processor [20], which stores multiple thread preemption contexts for executing Esterel. STARPro's hardware only allows upto four levels of nested preemptions per thread and it preallocates the hardware for each thread.…”

Section: Arpret Architecturementioning

confidence: 99%

Predictable multithreading of embedded applications using PRET-C

Andalam

Roop

Girault

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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We propose a new language called Precision Timed C (PRET-C), for predictable and lightweight multithreading in C. PRET-C supports synchronous concurrency, preemption, and a high-level construct for logical time. In contrast to existing synchronous languages, PRET-C offers C-based shared memory communications between concurrent threads that is guaranteed to be thread safe. Due to the proposed synchronous semantics, the mapping of logical time to physical time can be achieved much more easily than with plain C, thanks to a Worst Case Reaction Time (WCRT) analyzer (not presented here). Associated to the PRET-C programming language, we present a dedicated target architecture, called ARPRET, which combines a hardware accelerator associated to an existing softcore processor. This allows us to improve the throughput while preserving the predictability. With extensive benchmarking, we then demonstrate that ARPRET not only achieves completely predictable execution of PRET-C programs, but also improves the throughput when compared to the pure software execution of PRET-C. The PRET-C software approach is also significantly more efficient in comparison to two other lightweight concurrent C variants (namely SC and Protothreads), as well as the well-known Esterel synchronous programming language.

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“…There have been various proposals on how to support concurrency in reactive processing, including sequentialization, parallel execution, and, most recently, multi-threading [26], [27], [28]. The latter one appears to be the most effective at this point, and significantly outperforms classical softwarebased execution strategies while using minimal resources.…”

Section: Synchronicity and Timing Predictabilitymentioning

confidence: 99%

WCRT algebra and interfaces for esterel-style synchronous processing

Mendler

Hanxleden

Traulsen

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-The synchronous model of computation together with a suitable execution platform facilitates system-level timing predictability. This paper introduces an algebraic framework for precisely capturing worst case reaction time (WCRT) characteristics for Esterel-style reactive processors with hardware-supported multithreading. This framework provides a formal grounding for the WCRT problem, and allows to improve upon earlier heuristics by accurately and modularly characterizing timing interfaces.

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STARPro — A new multithreaded direct execution platform for Esterel

Cited by 7 publications

References 8 publications

Building timing predictable embedded systems

Building timing predictable embedded systems

Predictable multithreading of embedded applications using PRET-C

WCRT algebra and interfaces for esterel-style synchronous processing

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